[v3,08/27] arm64: Add HDFGRTR_EL2 and HDFGWTR_EL2 layouts

Message ID	20230808114711.2013842-9-maz@kernel.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org> From: Marc Zyngier <maz@kernel.org> To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas <catalin.marinas@arm.com>, Eric Auger <eric.auger@redhat.com>, Mark Brown <broonie@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Will Deacon <will@kernel.org>, Alexandru Elisei <alexandru.elisei@arm.com>, Andre Przywara <andre.przywara@arm.com>, Chase Conklin <chase.conklin@arm.com>, Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>, Darren Hart <darren@os.amperecomputing.com>, Miguel Luis <miguel.luis@oracle.com>, James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Oliver Upton <oliver.upton@linux.dev>, Zenghui Yu <yuzenghui@huawei.com> Subject: [PATCH v3 08/27] arm64: Add HDFGRTR_EL2 and HDFGWTR_EL2 layouts Date: Tue, 8 Aug 2023 12:46:52 +0100 Message-Id: <20230808114711.2013842-9-maz@kernel.org> In-Reply-To: <20230808114711.2013842-1-maz@kernel.org> References: <20230808114711.2013842-1-maz@kernel.org> MIME-Version: 1.0 Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
Series	KVM: arm64: NV trap forwarding infrastructure \| expand [v3,00/27] KVM: arm64: NV trap forwarding infrastructure [v3,01/27] arm64: Add missing VA CMO encodings [v3,02/27] arm64: Add missing ERX*_EL1 encodings [v3,03/27] arm64: Add missing DC ZVA/GVA/GZVA encodings [v3,04/27] arm64: Add TLBI operation encodings [v3,05/27] arm64: Add AT operation encodings [v3,06/27] arm64: Add debug registers affected by HDFGxTR_EL2 [v3,07/27] arm64: Add missing BRB/CFP/DVP/CPP instructions [v3,08/27] arm64: Add HDFGRTR_EL2 and HDFGWTR_EL2 layouts [v3,09/27] arm64: Add feature detection for fine grained traps [v3,10/27] KVM: arm64: Correctly handle ACCDATA_EL1 traps [v3,11/27] KVM: arm64: Add missing HCR_EL2 trap bits [v3,12/27] KVM: arm64: nv: Add FGT registers [v3,13/27] KVM: arm64: Restructure FGT register switching [v3,14/27] KVM: arm64: nv: Add trap forwarding infrastructure [v3,15/27] KVM: arm64: nv: Add trap forwarding for HCR_EL2 [v3,16/27] KVM: arm64: nv: Expose FEAT_EVT to nested guests [v3,17/27] KVM: arm64: nv: Add trap forwarding for MDCR_EL2 [v3,18/27] KVM: arm64: nv: Add trap forwarding for CNTHCTL_EL2 [v3,19/27] KVM: arm64: nv: Add fine grained trap forwarding infrastructure [v3,20/27] KVM: arm64: nv: Add trap forwarding for HFGxTR_EL2 [v3,21/27] KVM: arm64: nv: Add trap forwarding for HFGITR_EL2 [v3,22/27] KVM: arm64: nv: Add trap forwarding for HDFGxTR_EL2 [v3,23/27] KVM: arm64: nv: Add SVC trap forwarding [v3,24/27] KVM: arm64: nv: Add switching support for HFGxTR/HDFGxTR [v3,25/27] KVM: arm64: nv: Expose FGT to nested guests [v3,26/27] KVM: arm64: Move HCRX_EL2 switch to load/put on VHE systems [v3,27/27] KVM: arm64: nv: Add support for HCRX_EL2

Message ID

20230808114711.2013842-9-maz@kernel.org (mailing list archive)

State

New, archived

Headers

From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev,
	kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Eric Auger <eric.auger@redhat.com>,
	Mark Brown <broonie@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Will Deacon <will@kernel.org>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Andre Przywara <andre.przywara@arm.com>,
	Chase Conklin <chase.conklin@arm.com>,
	Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
	Darren Hart <darren@os.amperecomputing.com>,
	Miguel Luis <miguel.luis@oracle.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v3 08/27] arm64: Add HDFGRTR_EL2 and HDFGWTR_EL2 layouts
Date: Tue,  8 Aug 2023 12:46:52 +0100
Message-Id: <20230808114711.2013842-9-maz@kernel.org>
In-Reply-To: <20230808114711.2013842-1-maz@kernel.org>
References: <20230808114711.2013842-1-maz@kernel.org>
MIME-Version: 1.0
Precedence: list
Content-Type: text/plain; charset="us-ascii"
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Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
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 linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org

Series

KVM: arm64: NV trap forwarding infrastructure | expand

Commit Message

Marc Zyngier Aug. 8, 2023, 11:46 a.m. UTC

As we're about to implement full support for FEAT_FGT, add the
full HDFGRTR_EL2 and HDFGWTR_EL2 layouts.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Miguel Luis <miguel.luis@oracle.com>
---
 arch/arm64/include/asm/sysreg.h |   2 -
 arch/arm64/tools/sysreg         | 129 ++++++++++++++++++++++++++++++++
 2 files changed, 129 insertions(+), 2 deletions(-)

Comments

Jing Zhang Aug. 11, 2023, 3:19 a.m. UTC | #1

Hi Marc,

On Tue, Aug 8, 2023 at 4:47 AM Marc Zyngier <maz@kernel.org> wrote:
>
> As we're about to implement full support for FEAT_FGT, add the
> full HDFGRTR_EL2 and HDFGWTR_EL2 layouts.
>
> Reviewed-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> Reviewed-by: Miguel Luis <miguel.luis@oracle.com>
> ---
>  arch/arm64/include/asm/sysreg.h |   2 -
>  arch/arm64/tools/sysreg         | 129 ++++++++++++++++++++++++++++++++
>  2 files changed, 129 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 6d9d7ac4b31c..043c677e9f04 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -495,8 +495,6 @@
>  #define SYS_VTCR_EL2                   sys_reg(3, 4, 2, 1, 2)
>
>  #define SYS_TRFCR_EL2                  sys_reg(3, 4, 1, 2, 1)
> -#define SYS_HDFGRTR_EL2                        sys_reg(3, 4, 3, 1, 4)
> -#define SYS_HDFGWTR_EL2                        sys_reg(3, 4, 3, 1, 5)
>  #define SYS_HAFGRTR_EL2                        sys_reg(3, 4, 3, 1, 6)
>  #define SYS_SPSR_EL2                   sys_reg(3, 4, 4, 0, 0)
>  #define SYS_ELR_EL2                    sys_reg(3, 4, 4, 0, 1)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 65866bf819c3..2517ef7c21cf 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -2156,6 +2156,135 @@ Field   1       ICIALLU
>  Field  0       ICIALLUIS
>  EndSysreg
>
> +Sysreg HDFGRTR_EL2     3       4       3       1       4
> +Field  63      PMBIDR_EL1
> +Field  62      nPMSNEVFR_EL1
> +Field  61      nBRBDATA
> +Field  60      nBRBCTL
> +Field  59      nBRBIDR
> +Field  58      PMCEIDn_EL0
> +Field  57      PMUSERENR_EL0
> +Field  56      TRBTRG_EL1
> +Field  55      TRBSR_EL1
> +Field  54      TRBPTR_EL1
> +Field  53      TRBMAR_EL1
> +Field  52      TRBLIMITR_EL1
> +Field  51      TRBIDR_EL1
> +Field  50      TRBBASER_EL1
> +Res0   49
> +Field  48      TRCVICTLR
> +Field  47      TRCSTATR
> +Field  46      TRCSSCSRn
> +Field  45      TRCSEQSTR
> +Field  44      TRCPRGCTLR
> +Field  43      TRCOSLSR
> +Res0   42
> +Field  41      TRCIMSPECn
> +Field  40      TRCID
> +Res0   39:38
> +Field  37      TRCCNTVRn
> +Field  36      TRCCLAIM
> +Field  35      TRCAUXCTLR
> +Field  34      TRCAUTHSTATUS
> +Field  33      TRC
> +Field  32      PMSLATFR_EL1
> +Field  31      PMSIRR_EL1
> +Field  30      PMSIDR_EL1
> +Field  29      PMSICR_EL1
> +Field  28      PMSFCR_EL1
> +Field  27      PMSEVFR_EL1
> +Field  26      PMSCR_EL1
> +Field  25      PMBSR_EL1
> +Field  24      PMBPTR_EL1
> +Field  23      PMBLIMITR_EL1
> +Field  22      PMMIR_EL1
> +Res0   21:20
> +Field  19      PMSELR_EL0
> +Field  18      PMOVS
> +Field  17      PMINTEN
> +Field  16      PMCNTEN
> +Field  15      PMCCNTR_EL0
> +Field  14      PMCCFILTR_EL0
> +Field  13      PMEVTYPERn_EL0
> +Field  12      PMEVCNTRn_EL0
> +Field  11      OSDLR_EL1
> +Field  10      OSECCR_EL1
> +Field  9       OSLSR_EL1
> +Res0   8
> +Field  7       DBGPRCR_EL1
> +Field  6       DBGAUTHSTATUS_EL1
> +Field  5       DBGCLAIM
> +Field  4       MDSCR_EL1
> +Field  3       DBGWVRn_EL1
> +Field  2       DBGWCRn_EL1
> +Field  1       DBGBVRn_EL1
> +Field  0       DBGBCRn_EL1
> +EndSysreg
> +
> +Sysreg HDFGWTR_EL2     3       4       3       1       5
> +Res0   63
> +Field  62      nPMSNEVFR_EL1
> +Field  61      nBRBDATA
> +Field  60      nBRBCTL
> +Res0   59:58
> +Field  57      PMUSERENR_EL0
> +Field  56      TRBTRG_EL1
> +Field  55      TRBSR_EL1
> +Field  54      TRBPTR_EL1
> +Field  53      TRBMAR_EL1
> +Field  52      TRBLIMITR_EL1
> +Res0   51
> +Field  50      TRBBASER_EL1
> +Field  49      TRFCR_EL1
> +Field  48      TRCVICTLR
> +Res0   47
> +Field  46      TRCSSCSRn
> +Field  45      TRCSEQSTR
> +Field  44      TRCPRGCTLR
> +Res0   43
> +Field  42      TRCOSLAR
> +Field  41      TRCIMSPECn
> +Res0   40:38
> +Field  37      TRCCNTVRn
> +Field  36      TRCCLAIM
> +Field  35      TRCAUXCTLR
> +Res0   34
> +Field  33      TRC
> +Field  32      PMSLATFR_EL1
> +Field  31      PMSIRR_EL1
> +Res0   30
> +Field  29      PMSICR_EL1
> +Field  28      PMSFCR_EL1
> +Field  27      PMSEVFR_EL1
> +Field  26      PMSCR_EL1
> +Field  25      PMBSR_EL1
> +Field  24      PMBPTR_EL1
> +Field  23      PMBLIMITR_EL1
> +Res0   22
> +Field  21      PMCR_EL0
> +Field  20      PMSWINC_EL0
> +Field  19      PMSELR_EL0
> +Field  18      PMOVS
> +Field  17      PMINTEN
> +Field  16      PMCNTEN
> +Field  15      PMCCNTR_EL0
> +Field  14      PMCCFILTR_EL0
> +Field  13      PMEVTYPERn_EL0
> +Field  12      PMEVCNTRn_EL0
> +Field  11      OSDLR_EL1
> +Field  10      OSECCR_EL1
> +Res0   9
> +Field  8       OSLAR_EL1
> +Field  7       DBGPRCR_EL1
> +Res0   6
> +Field  5       DBGCLAIM
> +Field  4       MDSCR_EL1
> +Field  3       DBGWVRn_EL1
> +Field  2       DBGWCRn_EL1
> +Field  1       DBGBVRn_EL1
> +Field  0       DBGBCRn_EL1
> +EndSysreg
> +
>  Sysreg ZCR_EL2 3       4       1       2       0
>  Fields ZCR_ELx
>  EndSysreg
> --
> 2.34.1
>
>

Reviewed-by: Jing Zhang <jingzhangos@google.com>

Jing

Eric Auger Aug. 14, 2023, 12:32 p.m. UTC | #2

Hi Marc,

On 8/8/23 13:46, Marc Zyngier wrote:
> As we're about to implement full support for FEAT_FGT, add the
> full HDFGRTR_EL2 and HDFGWTR_EL2 layouts.
>
> Reviewed-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> Reviewed-by: Miguel Luis <miguel.luis@oracle.com>
> ---
>  arch/arm64/include/asm/sysreg.h |   2 -
>  arch/arm64/tools/sysreg         | 129 ++++++++++++++++++++++++++++++++
>  2 files changed, 129 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 6d9d7ac4b31c..043c677e9f04 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -495,8 +495,6 @@
>  #define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)
>  
>  #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
> -#define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
> -#define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
>  #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
>  #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
>  #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 65866bf819c3..2517ef7c21cf 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -2156,6 +2156,135 @@ Field	1	ICIALLU
>  Field	0	ICIALLUIS
>  EndSysreg
>  
> +Sysreg HDFGRTR_EL2	3	4	3	1	4
> +Field	63	PMBIDR_EL1
> +Field	62	nPMSNEVFR_EL1
> +Field	61	nBRBDATA
> +Field	60	nBRBCTL
> +Field	59	nBRBIDR
> +Field	58	PMCEIDn_EL0
> +Field	57	PMUSERENR_EL0
> +Field	56	TRBTRG_EL1
> +Field	55	TRBSR_EL1
> +Field	54	TRBPTR_EL1
> +Field	53	TRBMAR_EL1
> +Field	52	TRBLIMITR_EL1
> +Field	51	TRBIDR_EL1
> +Field	50	TRBBASER_EL1
> +Res0	49
> +Field	48	TRCVICTLR
> +Field	47	TRCSTATR
> +Field	46	TRCSSCSRn
> +Field	45	TRCSEQSTR
> +Field	44	TRCPRGCTLR
> +Field	43	TRCOSLSR
> +Res0	42
> +Field	41	TRCIMSPECn
> +Field	40	TRCID
> +Res0	39:38
> +Field	37	TRCCNTVRn
> +Field	36	TRCCLAIM
> +Field	35	TRCAUXCTLR
> +Field	34	TRCAUTHSTATUS
> +Field	33	TRC
> +Field	32	PMSLATFR_EL1
> +Field	31	PMSIRR_EL1
> +Field	30	PMSIDR_EL1
> +Field	29	PMSICR_EL1
> +Field	28	PMSFCR_EL1
> +Field	27	PMSEVFR_EL1
> +Field	26	PMSCR_EL1
> +Field	25	PMBSR_EL1
> +Field	24	PMBPTR_EL1
> +Field	23	PMBLIMITR_EL1
> +Field	22	PMMIR_EL1
> +Res0	21:20
> +Field	19	PMSELR_EL0
> +Field	18	PMOVS
> +Field	17	PMINTEN
> +Field	16	PMCNTEN
> +Field	15	PMCCNTR_EL0
> +Field	14	PMCCFILTR_EL0
> +Field	13	PMEVTYPERn_EL0
> +Field	12	PMEVCNTRn_EL0
> +Field	11	OSDLR_EL1
> +Field	10	OSECCR_EL1
> +Field	9	OSLSR_EL1
> +Res0	8
> +Field	7	DBGPRCR_EL1
> +Field	6	DBGAUTHSTATUS_EL1
> +Field	5	DBGCLAIM
> +Field	4	MDSCR_EL1
> +Field	3	DBGWVRn_EL1
> +Field	2	DBGWCRn_EL1
> +Field	1	DBGBVRn_EL1
> +Field	0	DBGBCRn_EL1
> +EndSysreg
> +
> +Sysreg HDFGWTR_EL2	3	4	3	1	5
> +Res0	63
> +Field	62	nPMSNEVFR_EL1
> +Field	61	nBRBDATA
> +Field	60	nBRBCTL
> +Res0	59:58
> +Field	57	PMUSERENR_EL0
> +Field	56	TRBTRG_EL1
> +Field	55	TRBSR_EL1
> +Field	54	TRBPTR_EL1
> +Field	53	TRBMAR_EL1
> +Field	52	TRBLIMITR_EL1
> +Res0	51
> +Field	50	TRBBASER_EL1
> +Field	49	TRFCR_EL1
> +Field	48	TRCVICTLR
> +Res0	47
> +Field	46	TRCSSCSRn
> +Field	45	TRCSEQSTR
> +Field	44	TRCPRGCTLR
> +Res0	43
> +Field	42	TRCOSLAR
> +Field	41	TRCIMSPECn
> +Res0	40:38
> +Field	37	TRCCNTVRn
> +Field	36	TRCCLAIM
> +Field	35	TRCAUXCTLR
> +Res0	34
> +Field	33	TRC
> +Field	32	PMSLATFR_EL1
> +Field	31	PMSIRR_EL1
> +Res0	30
> +Field	29	PMSICR_EL1
> +Field	28	PMSFCR_EL1
> +Field	27	PMSEVFR_EL1
> +Field	26	PMSCR_EL1
> +Field	25	PMBSR_EL1
> +Field	24	PMBPTR_EL1
> +Field	23	PMBLIMITR_EL1
> +Res0	22
> +Field	21	PMCR_EL0
> +Field	20	PMSWINC_EL0
> +Field	19	PMSELR_EL0
> +Field	18	PMOVS
> +Field	17	PMINTEN
> +Field	16	PMCNTEN
> +Field	15	PMCCNTR_EL0
> +Field	14	PMCCFILTR_EL0
> +Field	13	PMEVTYPERn_EL0
> +Field	12	PMEVCNTRn_EL0
> +Field	11	OSDLR_EL1
> +Field	10	OSECCR_EL1
> +Res0	9
> +Field	8	OSLAR_EL1
> +Field	7	DBGPRCR_EL1
> +Res0	6
> +Field	5	DBGCLAIM
> +Field	4	MDSCR_EL1
> +Field	3	DBGWVRn_EL1
> +Field	2	DBGWCRn_EL1
> +Field	1	DBGBVRn_EL1
> +Field	0	DBGBCRn_EL1
> +EndSysreg
> +
>  Sysreg	ZCR_EL2	3	4	1	2	0
>  Fields	ZCR_ELx
>  EndSysreg

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6d9d7ac4b31c..043c677e9f04 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -495,8 +495,6 @@ 
 #define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)
 
 #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
-#define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
-#define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
 #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
 #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 65866bf819c3..2517ef7c21cf 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2156,6 +2156,135 @@  Field	1	ICIALLU
 Field	0	ICIALLUIS
 EndSysreg
 
+Sysreg HDFGRTR_EL2	3	4	3	1	4
+Field	63	PMBIDR_EL1
+Field	62	nPMSNEVFR_EL1
+Field	61	nBRBDATA
+Field	60	nBRBCTL
+Field	59	nBRBIDR
+Field	58	PMCEIDn_EL0
+Field	57	PMUSERENR_EL0
+Field	56	TRBTRG_EL1
+Field	55	TRBSR_EL1
+Field	54	TRBPTR_EL1
+Field	53	TRBMAR_EL1
+Field	52	TRBLIMITR_EL1
+Field	51	TRBIDR_EL1
+Field	50	TRBBASER_EL1
+Res0	49
+Field	48	TRCVICTLR
+Field	47	TRCSTATR
+Field	46	TRCSSCSRn
+Field	45	TRCSEQSTR
+Field	44	TRCPRGCTLR
+Field	43	TRCOSLSR
+Res0	42
+Field	41	TRCIMSPECn
+Field	40	TRCID
+Res0	39:38
+Field	37	TRCCNTVRn
+Field	36	TRCCLAIM
+Field	35	TRCAUXCTLR
+Field	34	TRCAUTHSTATUS
+Field	33	TRC
+Field	32	PMSLATFR_EL1
+Field	31	PMSIRR_EL1
+Field	30	PMSIDR_EL1
+Field	29	PMSICR_EL1
+Field	28	PMSFCR_EL1
+Field	27	PMSEVFR_EL1
+Field	26	PMSCR_EL1
+Field	25	PMBSR_EL1
+Field	24	PMBPTR_EL1
+Field	23	PMBLIMITR_EL1
+Field	22	PMMIR_EL1
+Res0	21:20
+Field	19	PMSELR_EL0
+Field	18	PMOVS
+Field	17	PMINTEN
+Field	16	PMCNTEN
+Field	15	PMCCNTR_EL0
+Field	14	PMCCFILTR_EL0
+Field	13	PMEVTYPERn_EL0
+Field	12	PMEVCNTRn_EL0
+Field	11	OSDLR_EL1
+Field	10	OSECCR_EL1
+Field	9	OSLSR_EL1
+Res0	8
+Field	7	DBGPRCR_EL1
+Field	6	DBGAUTHSTATUS_EL1
+Field	5	DBGCLAIM
+Field	4	MDSCR_EL1
+Field	3	DBGWVRn_EL1
+Field	2	DBGWCRn_EL1
+Field	1	DBGBVRn_EL1
+Field	0	DBGBCRn_EL1
+EndSysreg
+
+Sysreg HDFGWTR_EL2	3	4	3	1	5
+Res0	63
+Field	62	nPMSNEVFR_EL1
+Field	61	nBRBDATA
+Field	60	nBRBCTL
+Res0	59:58
+Field	57	PMUSERENR_EL0
+Field	56	TRBTRG_EL1
+Field	55	TRBSR_EL1
+Field	54	TRBPTR_EL1
+Field	53	TRBMAR_EL1
+Field	52	TRBLIMITR_EL1
+Res0	51
+Field	50	TRBBASER_EL1
+Field	49	TRFCR_EL1
+Field	48	TRCVICTLR
+Res0	47
+Field	46	TRCSSCSRn
+Field	45	TRCSEQSTR
+Field	44	TRCPRGCTLR
+Res0	43
+Field	42	TRCOSLAR
+Field	41	TRCIMSPECn
+Res0	40:38
+Field	37	TRCCNTVRn
+Field	36	TRCCLAIM
+Field	35	TRCAUXCTLR
+Res0	34
+Field	33	TRC
+Field	32	PMSLATFR_EL1
+Field	31	PMSIRR_EL1
+Res0	30
+Field	29	PMSICR_EL1
+Field	28	PMSFCR_EL1
+Field	27	PMSEVFR_EL1
+Field	26	PMSCR_EL1
+Field	25	PMBSR_EL1
+Field	24	PMBPTR_EL1
+Field	23	PMBLIMITR_EL1
+Res0	22
+Field	21	PMCR_EL0
+Field	20	PMSWINC_EL0
+Field	19	PMSELR_EL0
+Field	18	PMOVS
+Field	17	PMINTEN
+Field	16	PMCNTEN
+Field	15	PMCCNTR_EL0
+Field	14	PMCCFILTR_EL0
+Field	13	PMEVTYPERn_EL0
+Field	12	PMEVCNTRn_EL0
+Field	11	OSDLR_EL1
+Field	10	OSECCR_EL1
+Res0	9
+Field	8	OSLAR_EL1
+Field	7	DBGPRCR_EL1
+Res0	6
+Field	5	DBGCLAIM
+Field	4	MDSCR_EL1
+Field	3	DBGWVRn_EL1
+Field	2	DBGWCRn_EL1
+Field	1	DBGBVRn_EL1
+Field	0	DBGBCRn_EL1
+EndSysreg
+
 Sysreg	ZCR_EL2	3	4	1	2	0
 Fields	ZCR_ELx
 EndSysreg

[v3,08/27] arm64: Add HDFGRTR_EL2 and HDFGWTR_EL2 layouts

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Patch