| Message ID | 1692717141-32743-2-git-send-email-quic_krichai@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: qcom: Add support for OPP | expand |
On 22.08.2023 17:12, Krishna chaitanya chundru wrote: > PCIe needs to choose the appropriate performance state of RPMH power > domain based upon the PCIe gen speed. > > Adding the Operating Performance Points table allows to adjust power domain > performance state, depending on the PCIe gen speed. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- I only got patches 1, 2 and 4 of this series. Please consider using the b4 tool [1], which takes care of all of the sending shenanigans for you. Konrad [1] https://b4.docs.kernel.org/en/latest/index.html
On Tue, Aug 22, 2023 at 08:42:18PM +0530, Krishna chaitanya chundru wrote: > PCIe needs to choose the appropriate performance state of RPMH power > domain based upon the PCIe gen speed. > > Adding the Operating Performance Points table allows to adjust power domain > performance state, depending on the PCIe gen speed. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 81971be4..779339c 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -121,6 +121,10 @@ properties: > description: GPIO controlled connection to WAKE# signal > maxItems: 1 > > + operating-points-v2: true > + opp-table: > + type: object > + > required: > - compatible > - reg > -- > 2.7.4 >
On 8/22/2023 9:36 PM, Konrad Dybcio wrote: > On 22.08.2023 17:12, Krishna chaitanya chundru wrote: >> PCIe needs to choose the appropriate performance state of RPMH power >> domain based upon the PCIe gen speed. >> >> Adding the Operating Performance Points table allows to adjust power domain >> performance state, depending on the PCIe gen speed. >> >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> --- > I only got patches 1, 2 and 4 of this series. > > Please consider using the b4 tool [1], which takes care of > all of the sending shenanigans for you. > > Konrad > > [1] https://b4.docs.kernel.org/en/latest/index.html Sorry, for late reply I have taken care of this in next patch series.
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 81971be4..779339c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -121,6 +121,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + operating-points-v2: true + opp-table: + type: object + required: - compatible - reg