| Message ID | 20230823085031.27252-2-quic_luoj@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | add clock controller of qca8386/qca8084 | expand |
Quoting Luo Jie (2023-08-23 01:50:28) > diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c > index fc4735f74f0f..5e08c026ca4a 100644 > --- a/drivers/clk/qcom/clk-branch.c > +++ b/drivers/clk/qcom/clk-branch.c > @@ -153,3 +153,10 @@ const struct clk_ops clk_branch_simple_ops = { > .is_enabled = clk_is_enabled_regmap, > }; > EXPORT_SYMBOL_GPL(clk_branch_simple_ops); > + > +const struct clk_ops clk_branch2_mdio_ops = { > + .prepare = clk_branch2_enable, > + .unprepare = clk_branch2_disable, > + .is_prepared = clk_is_enabled_regmap, > +}; > +EXPORT_SYMBOL_GPL(clk_branch2_mdio_ops); I'd call it clk_branch2_simple_prepare_ops or something like that. There's nothing mdio specific about it.
On 8/24/2023 2:04 AM, Stephen Boyd wrote: > Quoting Luo Jie (2023-08-23 01:50:28) >> diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c >> index fc4735f74f0f..5e08c026ca4a 100644 >> --- a/drivers/clk/qcom/clk-branch.c >> +++ b/drivers/clk/qcom/clk-branch.c >> @@ -153,3 +153,10 @@ const struct clk_ops clk_branch_simple_ops = { >> .is_enabled = clk_is_enabled_regmap, >> }; >> EXPORT_SYMBOL_GPL(clk_branch_simple_ops); >> + >> +const struct clk_ops clk_branch2_mdio_ops = { >> + .prepare = clk_branch2_enable, >> + .unprepare = clk_branch2_disable, >> + .is_prepared = clk_is_enabled_regmap, >> +}; >> +EXPORT_SYMBOL_GPL(clk_branch2_mdio_ops); > > I'd call it clk_branch2_simple_prepare_ops or something like that. > There's nothing mdio specific about it. Thanks Stephen for the proposal. As for qcom clock controller, only the device accessed by MDIO bus has this kind of ops, the clk_branch2_mdio_ops can also imply that the MDIO bus is used for accessing the HW register, i think this is also the reason that Konrad suggested this ops name.
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index fc4735f74f0f..5e08c026ca4a 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -153,3 +153,10 @@ const struct clk_ops clk_branch_simple_ops = { .is_enabled = clk_is_enabled_regmap, }; EXPORT_SYMBOL_GPL(clk_branch_simple_ops); + +const struct clk_ops clk_branch2_mdio_ops = { + .prepare = clk_branch2_enable, + .unprepare = clk_branch2_disable, + .is_prepared = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL_GPL(clk_branch2_mdio_ops); diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 0cf800b9d08d..4b006e8eec5e 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -85,6 +85,7 @@ extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; extern const struct clk_ops clk_branch2_aon_ops; +extern const struct clk_ops clk_branch2_mdio_ops; #define to_clk_branch(_hw) \ container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
Add the clk_branch2_mdio_ops for supporting clock controller where the hardware register is accessed by MDIO bus, and the spin lock can't be used because of sleep during the MDIO operation. The clock is enabled by the .prepare instead of .enable when the clk_branch2_mdio_ops is used. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- drivers/clk/qcom/clk-branch.c | 7 +++++++ drivers/clk/qcom/clk-branch.h | 1 + 2 files changed, 8 insertions(+)