diff mbox series

[V2,1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574

Message ID 20230825091234.32713-2-quic_devipriy@quicinc.com (mailing list archive)
State Changes Requested, archived
Headers show
Series Add NSS clock controller support for IPQ9574 | expand

Commit Message

Devi Priya Aug. 25, 2023, 9:12 a.m. UTC 
Add support for NSS Huayra alpha pll found on ipq9574 SoCs.
Programming sequence is the same as that of Huayra type Alpha PLL,
so we can re-use the same.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Changes in V2:
	- Picked up the R-b tag

 drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++
 drivers/clk/qcom/clk-alpha-pll.h |  1 +
 2 files changed, 13 insertions(+)

Comments

Stephen Boyd Aug. 25, 2023, 8:58 p.m. UTC | #1 
Quoting Devi Priya (2023-08-25 02:12:28)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index e4ef645f65d1..1c2a72840cd2 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -228,6 +228,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
>                 [PLL_OFF_ALPHA_VAL] = 0x24,
>                 [PLL_OFF_ALPHA_VAL_U] = 0x28,
>         },
> +

Why the extra newline? All other types aren't this way.

> +       [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] =  {
> +               [PLL_OFF_L_VAL] = 0x04,
> +               [PLL_OFF_ALPHA_VAL] = 0x08,
> +               [PLL_OFF_TEST_CTL] = 0x0c,
> +               [PLL_OFF_TEST_CTL_U] = 0x10,
> +               [PLL_OFF_USER_CTL] = 0x14,
> +               [PLL_OFF_CONFIG_CTL] = 0x18,
> +               [PLL_OFF_CONFIG_CTL_U] = 0x1c,
> +               [PLL_OFF_STATUS] = 0x20,
> +       },
> +
Devi Priya Aug. 29, 2023, 3:28 a.m. UTC | #2 
On 8/26/2023 2:28 AM, Stephen Boyd wrote:
> Quoting Devi Priya (2023-08-25 02:12:28)
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>> index e4ef645f65d1..1c2a72840cd2 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -228,6 +228,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
>>                  [PLL_OFF_ALPHA_VAL] = 0x24,
>>                  [PLL_OFF_ALPHA_VAL_U] = 0x28,
>>          },
>> +
> 
> Why the extra newline? All other types aren't this way.
Sure, will drop it in V3

Thanks,
Devi Priya
> 
>> +       [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] =  {
>> +               [PLL_OFF_L_VAL] = 0x04,
>> +               [PLL_OFF_ALPHA_VAL] = 0x08,
>> +               [PLL_OFF_TEST_CTL] = 0x0c,
>> +               [PLL_OFF_TEST_CTL_U] = 0x10,
>> +               [PLL_OFF_USER_CTL] = 0x14,
>> +               [PLL_OFF_CONFIG_CTL] = 0x18,
>> +               [PLL_OFF_CONFIG_CTL_U] = 0x1c,
>> +               [PLL_OFF_STATUS] = 0x20,
>> +       },
>> +
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index e4ef645f65d1..1c2a72840cd2 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -228,6 +228,18 @@  const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_ALPHA_VAL] = 0x24,
 		[PLL_OFF_ALPHA_VAL_U] = 0x28,
 	},
+
+	[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] =  {
+		[PLL_OFF_L_VAL] = 0x04,
+		[PLL_OFF_ALPHA_VAL] = 0x08,
+		[PLL_OFF_TEST_CTL] = 0x0c,
+		[PLL_OFF_TEST_CTL_U] = 0x10,
+		[PLL_OFF_USER_CTL] = 0x14,
+		[PLL_OFF_CONFIG_CTL] = 0x18,
+		[PLL_OFF_CONFIG_CTL_U] = 0x1c,
+		[PLL_OFF_STATUS] = 0x20,
+	},
+
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index e4bd863027ab..cb079a6ed96a 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -28,6 +28,7 @@  enum {
 	CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
 	CLK_ALPHA_PLL_TYPE_STROMER,
 	CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
+	CLK_ALPHA_PLL_TYPE_NSS_HUAYRA,
 	CLK_ALPHA_PLL_TYPE_MAX,
 };