diff mbox series

[08/10] target/tricore: Swap src and dst reg for RCRR_INSERT

Message ID 20230826160242.312052-9-kbastian@mail.uni-paderborn.de (mailing list archive)
State New, archived
Headers show
Series TriCore 1.6.2 insn and bugfixes | expand

Commit Message

Bastian Koppelmann Aug. 26, 2023, 4:02 p.m. UTC
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target/tricore/translate.c          | 8 ++++----
 tests/tcg/tricore/asm/macros.h      | 9 +++++++++
 tests/tcg/tricore/asm/test_insert.S | 5 +++++
 3 files changed, 18 insertions(+), 4 deletions(-)

Comments

Richard Henderson Aug. 27, 2023, 5:06 a.m. UTC | #1
On 8/26/23 09:02, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
>   target/tricore/translate.c          | 8 ++++----
>   tests/tcg/tricore/asm/macros.h      | 9 +++++++++
>   tests/tcg/tricore/asm/test_insert.S | 5 +++++
>   3 files changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index d13f85c03a..a68660b326 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -8225,12 +8225,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
>           temp2 = tcg_temp_new(); /* width*/
>           temp3 = tcg_temp_new(); /* pos */
>   
> -        CHECK_REG_PAIR(r3);
> +        CHECK_REG_PAIR(r2);

While it looks as if the end result is the same, it appears the macros used just above are 
wrong.  The field definitions for RCRR on page 1-4 do not match the field definitions for 
INSERT.RCRR on page 3-118.


r~
Bastian Koppelmann Aug. 27, 2023, 7:18 a.m. UTC | #2
On Sat, Aug 26, 2023 at 10:06:22PM -0700, Richard Henderson wrote:
> On 8/26/23 09:02, Bastian Koppelmann wrote:
> > Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> > ---
> >   target/tricore/translate.c          | 8 ++++----
> >   tests/tcg/tricore/asm/macros.h      | 9 +++++++++
> >   tests/tcg/tricore/asm/test_insert.S | 5 +++++
> >   3 files changed, 18 insertions(+), 4 deletions(-)
> > 
> > diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> > index d13f85c03a..a68660b326 100644
> > --- a/target/tricore/translate.c
> > +++ b/target/tricore/translate.c
> > @@ -8225,12 +8225,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
> >           temp2 = tcg_temp_new(); /* width*/
> >           temp3 = tcg_temp_new(); /* pos */
> > -        CHECK_REG_PAIR(r3);
> > +        CHECK_REG_PAIR(r2);
> 
> While it looks as if the end result is the same, it appears the macros used
> just above are wrong.  The field definitions for RCRR on page 1-4 do not
> match the field definitions for INSERT.RCRR on page 3-118.

Looks correct to me. I guess it is confusing that RCRR on page 1-4 uses s1, s2,
etc., and d for the reg names, while INSERT.RCRR on page 3-118 enumerates the reg
names from a to d. So the "d" for dst from page 1-4 is not the same "d" on page
3-118.

Cheers,
Bastian
diff mbox series

Patch

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index d13f85c03a..a68660b326 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8225,12 +8225,12 @@  static void decode_32Bit_opc(DisasContext *ctx)
         temp2 = tcg_temp_new(); /* width*/
         temp3 = tcg_temp_new(); /* pos */
 
-        CHECK_REG_PAIR(r3);
+        CHECK_REG_PAIR(r2);
 
-        tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
-        tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+        tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
+        tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
 
-        gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
+        gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
         break;
 /* RCRW Format */
     case OPCM_32_RCRW_MASK_INSERT:
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 51f6191ef2..17e696bef5 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -169,6 +169,15 @@  test_ ## num:                                                    \
     insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2;   \
     )
 
+#define TEST_D_DIE(insn, num, result, rs1, imm1, rs2_lo, rs2_hi)\
+    TEST_CASE(num, DREG_CALC_RESULT, result,                    \
+    LI(DREG_RS1, rs1);                                          \
+    LI(EREG_RS2_LO, rs2_lo);                                    \
+    LI(EREG_RS2_HI, rs2_hi);                                    \
+    rstv;                                                       \
+    insn DREG_CALC_RESULT, DREG_RS1, imm1, EREG_RS2;            \
+    )
+
 #define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
     TEST_CASE(num, DREG_CALC_RESULT, result,                 \
     LI(DREG_RS1, rs1);                                       \
diff --git a/tests/tcg/tricore/asm/test_insert.S b/tests/tcg/tricore/asm/test_insert.S
index 3978810121..223d7ce796 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -15,4 +15,9 @@  _start:
 #                 |     |      |           |           |        |    |
     TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
 
+#                insn num   result       rs1     imm1      rs2_h       rs2_l
+#                 |    |      |           |        |         |           |
+    TEST_D_DIE(insert, 5, 0xe30c308d, 0xe30c308d ,0x3 , 0x00000000 ,0x00000000)
+    TEST_D_DIE(insert, 6, 0x669b0120, 0x669b2820 ,0x2 , 0x5530a1c7 ,0x3a2b0f67)
+
     TEST_PASSFAIL