diff mbox series

[05/31] clk: rockchip: rk3128: Fix aclk_peri_src parent

Message ID 20230829171647.187787-6-knaerzche@gmail.com (mailing list archive)
State New, archived
Headers show
Series Fix and improve Rockchip RK3128 support | expand

Commit Message

Alex Bee Aug. 29, 2023, 5:16 p.m. UTC 
From: Finley Xiao <finley.xiao@rock-chips.com>

According to the TRM there are no specific cpll_peri, gpll_div2_peri or
gpll_div3_peri gates, but a single clk_peri_src gate and the peri mux
directly connects to the plls respectivly the pll divider clocks.
Fix this by creating a single gated composite.

Also rename all occurrences of "aclk_peri_src*" to clk_peri_src, since it
is the parent for both peri aclks and hclks and that also matches the
naming in the TRM.

Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
[renamed aclk_peri_src -> clk_peri_src and added commit message]
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 drivers/clk/rockchip/clk-rk3128.c | 20 +++++++-------------
 1 file changed, 7 insertions(+), 13 deletions(-)

Comments

Krzysztof Kozlowski Aug. 29, 2023, 5:40 p.m. UTC | #1 
On 29/08/2023 19:16, Alex Bee wrote:
> From: Finley Xiao <finley.xiao@rock-chips.com>
> 
> According to the TRM there are no specific cpll_peri, gpll_div2_peri or
> gpll_div3_peri gates, but a single clk_peri_src gate and the peri mux
> directly connects to the plls respectivly the pll divider clocks.
> Fix this by creating a single gated composite.
> 
> Also rename all occurrences of "aclk_peri_src*" to clk_peri_src, since it
> is the parent for both peri aclks and hclks and that also matches the
> naming in the TRM.
> 
> Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
> [renamed aclk_peri_src -> clk_peri_src and added commit message]
> Signed-off-by: Alex Bee <knaerzche@gmail.com>

Please send fixes as separate patchset. Don't mix it with other work and
definitely it should not be in the middle of the patchset.

Best regards,
Krzysztof
Alex Bee Aug. 29, 2023, 6:36 p.m. UTC | #2 
Hi Krzysztof,

thanks for your quick feedback.

You're right: This series mixes up too many things. I'll split up and 
re-send.

(And fix my typos, indeed)

Best Regards,

Alex

Am 29.08.23 um 19:40 schrieb Krzysztof Kozlowski:
> On 29/08/2023 19:16, Alex Bee wrote:
>> From: Finley Xiao <finley.xiao@rock-chips.com>
>>
>> According to the TRM there are no specific cpll_peri, gpll_div2_peri or
>> gpll_div3_peri gates, but a single clk_peri_src gate and the peri mux
>> directly connects to the plls respectivly the pll divider clocks.
>> Fix this by creating a single gated composite.
>>
>> Also rename all occurrences of "aclk_peri_src*" to clk_peri_src, since it
>> is the parent for both peri aclks and hclks and that also matches the
>> naming in the TRM.
>>
>> Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
>> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
>> [renamed aclk_peri_src -> clk_peri_src and added commit message]
>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> Please send fixes as separate patchset. Don't mix it with other work and
> definitely it should not be in the middle of the patchset.
>
> Best regards,
> Krzysztof
>
diff mbox series

Patch

diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index aa53797dbfc1..fcacfe758829 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -138,7 +138,7 @@  PNAME(mux_pll_src_5plls_p)	= { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480
 PNAME(mux_pll_src_4plls_p)	= { "cpll", "gpll", "gpll_div2", "usb480m" };
 PNAME(mux_pll_src_3plls_p)	= { "cpll", "gpll", "gpll_div2" };
 
-PNAME(mux_aclk_peri_src_p)	= { "gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri" };
+PNAME(mux_clk_peri_src_p)	= { "gpll", "cpll", "gpll_div2", "gpll_div3" };
 PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "gpll_div2", "xin24m" };
 PNAME(mux_clk_cif_out_src_p)		= { "clk_cif_src", "xin24m" };
 PNAME(mux_sclk_vop_src_p)	= { "cpll", "gpll", "gpll_div2", "gpll_div3" };
@@ -275,23 +275,17 @@  static struct rockchip_clk_branch common_clk_branches[] __initdata = {
 			RK2928_CLKGATE_CON(0), 11, GFLAGS),
 
 	/* PD_PERI */
-	GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
+	COMPOSITE(0, "clk_peri_src", mux_clk_peri_src_p, 0,
+			RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
 			RK2928_CLKGATE_CON(2), 0, GFLAGS),
-	GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
-			RK2928_CLKGATE_CON(2), 0, GFLAGS),
-	GATE(0, "gpll_div2_peri", "gpll_div2", CLK_IGNORE_UNUSED,
-			RK2928_CLKGATE_CON(2), 0, GFLAGS),
-	GATE(0, "gpll_div3_peri", "gpll_div3", CLK_IGNORE_UNUSED,
-			RK2928_CLKGATE_CON(2), 0, GFLAGS),
-	COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
-			RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS),
-	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
+
+	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", 0,
 			RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 			RK2928_CLKGATE_CON(2), 3, GFLAGS),
-	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
+	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", 0,
 			RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 			RK2928_CLKGATE_CON(2), 2, GFLAGS),
-	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
+	GATE(ACLK_PERI, "aclk_peri", "clk_peri_src", 0,
 			RK2928_CLKGATE_CON(2), 1, GFLAGS),
 
 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,