| Message ID | 20230901092645.20522-3-quic_nsekar@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable IPQ5018 USB2 support | expand |
On Fri, 1 Sept 2023 at 12:27, Nitheesh Sekar <quic_nsekar@quicinc.com> wrote: > > Add phy init sequence and compatible string for IPQ5018 > chipset. > > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > --- > V3: > Dropped 0 delay inits. > Added static const type for m31_ipq5018_regs. > V2: > Updated the commit message. > --- > drivers/phy/qualcomm/phy-qcom-m31.c | 49 +++++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c > index ed08072ca032..ceee38695d7d 100644 > --- a/drivers/phy/qualcomm/phy-qcom-m31.c > +++ b/drivers/phy/qualcomm/phy-qcom-m31.c > @@ -82,6 +82,48 @@ struct m31_priv_data { > unsigned int nregs; > }; > > +static const struct m31_phy_regs m31_ipq5018_regs[] = { > + { C99 initializers, please? > + USB_PHY_CFG0, > + UTMI_PHY_OVERRIDE_EN > + }, > + { > + USB_PHY_UTMI_CTRL5, > + POR_EN, > + 15 > + }, > + { > + USB_PHY_FSEL_SEL, > + FREQ_SEL > + }, > + { > + USB_PHY_HS_PHY_CTRL_COMMON0, > + COMMONONN | FSEL | RETENABLEN > + }, > + { > + USB_PHY_REFCLK_CTRL, > + CLKCORE > + }, > + { > + USB_PHY_UTMI_CTRL5, > + POR_EN > + }, > + { > + USB_PHY_HS_PHY_CTRL2, > + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN > + }, > + { > + USB_PHY_UTMI_CTRL5 > + }, > + { > + USB_PHY_HS_PHY_CTRL2, > + USB2_SUSPEND_N | USB2_UTMI_CLK_EN > + }, > + { > + USB_PHY_CFG0 What is the value written? While it didn't make sense to write 0 delays, it is sensible to write 0 register values here. > + }, > +}; > + > struct m31_phy_regs m31_ipq5332_regs[] = { > { > USB_PHY_CFG0, > @@ -268,6 +310,12 @@ static int m31usb_phy_probe(struct platform_device *pdev) > return PTR_ERR_OR_ZERO(phy_provider); > } > > +static const struct m31_priv_data m31_ipq5018_data = { > + .ulpi_mode = false, > + .regs = m31_ipq5018_regs, > + .nregs = ARRAY_SIZE(m31_ipq5018_regs), > +}; > + > static const struct m31_priv_data m31_ipq5332_data = { > .ulpi_mode = false, > .regs = m31_ipq5332_regs, > @@ -275,6 +323,7 @@ static const struct m31_priv_data m31_ipq5332_data = { > }; > > static const struct of_device_id m31usb_phy_id_table[] = { > + { .compatible = "qcom,ipq5018-usb-hsphy", .data = &m31_ipq5018_data }, > { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data }, > { }, > }; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
On 9/2/2023 3:20 AM, Dmitry Baryshkov wrote: > On Fri, 1 Sept 2023 at 12:27, Nitheesh Sekar <quic_nsekar@quicinc.com> wrote: >> Add phy init sequence and compatible string for IPQ5018 >> chipset. >> >> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> >> --- >> V3: >> Dropped 0 delay inits. >> Added static const type for m31_ipq5018_regs. >> V2: >> Updated the commit message. >> --- >> drivers/phy/qualcomm/phy-qcom-m31.c | 49 +++++++++++++++++++++++++++++ >> 1 file changed, 49 insertions(+) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c >> index ed08072ca032..ceee38695d7d 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-m31.c >> +++ b/drivers/phy/qualcomm/phy-qcom-m31.c >> @@ -82,6 +82,48 @@ struct m31_priv_data { >> unsigned int nregs; >> }; >> >> +static const struct m31_phy_regs m31_ipq5018_regs[] = { >> + { > C99 initializers, please? Sorry. Missed it. Will update and post a new patchset. > >> + USB_PHY_CFG0, >> + UTMI_PHY_OVERRIDE_EN >> + }, >> + { >> + USB_PHY_UTMI_CTRL5, >> + POR_EN, >> + 15 >> + }, >> + { >> + USB_PHY_FSEL_SEL, >> + FREQ_SEL >> + }, >> + { >> + USB_PHY_HS_PHY_CTRL_COMMON0, >> + COMMONONN | FSEL | RETENABLEN >> + }, >> + { >> + USB_PHY_REFCLK_CTRL, >> + CLKCORE >> + }, >> + { >> + USB_PHY_UTMI_CTRL5, >> + POR_EN >> + }, >> + { >> + USB_PHY_HS_PHY_CTRL2, >> + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN >> + }, >> + { >> + USB_PHY_UTMI_CTRL5 >> + }, >> + { >> + USB_PHY_HS_PHY_CTRL2, >> + USB2_SUSPEND_N | USB2_UTMI_CLK_EN >> + }, >> + { >> + USB_PHY_CFG0 > What is the value written? While it didn't make sense to write 0 > delays, it is sensible to write 0 register values here. Value to be written is 0. I will update this. > >> + }, >> +}; >> + >> struct m31_phy_regs m31_ipq5332_regs[] = { >> { >> USB_PHY_CFG0, >> @@ -268,6 +310,12 @@ static int m31usb_phy_probe(struct platform_device *pdev) >> return PTR_ERR_OR_ZERO(phy_provider); >> } >> >> +static const struct m31_priv_data m31_ipq5018_data = { >> + .ulpi_mode = false, >> + .regs = m31_ipq5018_regs, >> + .nregs = ARRAY_SIZE(m31_ipq5018_regs), >> +}; >> + >> static const struct m31_priv_data m31_ipq5332_data = { >> .ulpi_mode = false, >> .regs = m31_ipq5332_regs, >> @@ -275,6 +323,7 @@ static const struct m31_priv_data m31_ipq5332_data = { >> }; >> >> static const struct of_device_id m31usb_phy_id_table[] = { >> + { .compatible = "qcom,ipq5018-usb-hsphy", .data = &m31_ipq5018_data }, >> { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data }, >> { }, >> }; >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, >> a Linux Foundation Collaborative Project >> >
diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c index ed08072ca032..ceee38695d7d 100644 --- a/drivers/phy/qualcomm/phy-qcom-m31.c +++ b/drivers/phy/qualcomm/phy-qcom-m31.c @@ -82,6 +82,48 @@ struct m31_priv_data { unsigned int nregs; }; +static const struct m31_phy_regs m31_ipq5018_regs[] = { + { + USB_PHY_CFG0, + UTMI_PHY_OVERRIDE_EN + }, + { + USB_PHY_UTMI_CTRL5, + POR_EN, + 15 + }, + { + USB_PHY_FSEL_SEL, + FREQ_SEL + }, + { + USB_PHY_HS_PHY_CTRL_COMMON0, + COMMONONN | FSEL | RETENABLEN + }, + { + USB_PHY_REFCLK_CTRL, + CLKCORE + }, + { + USB_PHY_UTMI_CTRL5, + POR_EN + }, + { + USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN + }, + { + USB_PHY_UTMI_CTRL5 + }, + { + USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N | USB2_UTMI_CLK_EN + }, + { + USB_PHY_CFG0 + }, +}; + struct m31_phy_regs m31_ipq5332_regs[] = { { USB_PHY_CFG0, @@ -268,6 +310,12 @@ static int m31usb_phy_probe(struct platform_device *pdev) return PTR_ERR_OR_ZERO(phy_provider); } +static const struct m31_priv_data m31_ipq5018_data = { + .ulpi_mode = false, + .regs = m31_ipq5018_regs, + .nregs = ARRAY_SIZE(m31_ipq5018_regs), +}; + static const struct m31_priv_data m31_ipq5332_data = { .ulpi_mode = false, .regs = m31_ipq5332_regs, @@ -275,6 +323,7 @@ static const struct m31_priv_data m31_ipq5332_data = { }; static const struct of_device_id m31usb_phy_id_table[] = { + { .compatible = "qcom,ipq5018-usb-hsphy", .data = &m31_ipq5018_data }, { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data }, { }, };
Add phy init sequence and compatible string for IPQ5018 chipset. Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> --- V3: Dropped 0 delay inits. Added static const type for m31_ipq5018_regs. V2: Updated the commit message. --- drivers/phy/qualcomm/phy-qcom-m31.c | 49 +++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+)