[2/5] dt-bindings: phy: Add qcom,sdx75-qmp-usb3-uni schema file

Commit Message

Rohit Agarwal Sept. 5, 2023, 4:43 a.m. UTC

Add a dt-binding schema for SDX75 SoC.

Signed-off-by: Rohit Agarwal <[e-mail]>
---
 .../bindings/phy/qcom,sdx75-qmp-usb3-uni-phy.yaml  | 106 +++++++++++++++++++++
 1 file changed, 106 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom,sdx75-qmp-usb3-uni-phy.yaml

Comments

Rob Herring (Arm) Sept. 5, 2023, 5:48 p.m. UTC | #1

On Tue, 05 Sep 2023 10:13:45 +0530, Rohit Agarwal wrote:
> Add a dt-binding schema for SDX75 SoC.
> 
> Signed-off-by: Rohit Agarwal <[e-mail]>
> ---
>  .../bindings/phy/qcom,sdx75-qmp-usb3-uni-phy.yaml  | 106 +++++++++++++++++++++
>  1 file changed, 106 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom,sdx75-qmp-usb3-uni-phy.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/qcom,sdx75-qmp-usb3-uni-phy.example.dts:18:18: fatal error: dt-bindings/clock/qcom,gcc-sdx75.h: No such file or directory
   18 |         #include <dt-bindings/clock/qcom,gcc-sdx75.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/phy/qcom,sdx75-qmp-usb3-uni-phy.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1500: dt_binding_check] Error 2
make: *** [Makefile:234: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[e-mail]

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Patch

diff --git a/Documentation/devicetree/bindings/phy/qcom,sdx75-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sdx75-qmp-usb3-uni-phy.yaml
new file mode 100644
index 0000000..2ae0710
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,sdx75-qmp-usb3-uni-phy.yaml
@@ -0,0 +1,106 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,sdx75-qmp-usb3-uni-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QMP PHY controller (USB, SDX75)
+
+maintainers:
+  - Vinod Koul <[e-mail]>
+
+description:
+  The QMP PHY controller supports physical layer functionality for a number of
+  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+properties:
+  compatible:
+    enum:
+      - qcom,sdx75-qmp-usb3-uni-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    items:
+      - const: aux
+      - const: cfg_ahb
+      - const: ref
+      - const: pipe
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 2
+
+  reset-names:
+    items:
+      - const: phy
+      - const: common
+
+  vdda-phy-supply: true
+
+  vdda-pll-supply: true
+
+  "#clock-cells":
+    const: 0
+
+  clock-output-names:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+  - resets
+  - reset-names
+  - vdda-phy-supply
+  - vdda-pll-supply
+  - "#clock-cells"
+  - clock-output-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sdx75.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+
+    phy@ff6000 {
+      compatible = "qcom,sdx75-qmp-usb3-uni-phy";
+      reg = <0x0ff6000 0x2000>;
+
+      clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+               <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+               <&gcc GCC_USB2_CLKREF_EN>,
+               <&gcc GCC_USB3_PHY_PIPE_CLK>;
+      clock-names = "aux",
+                    "cfg_ahb",
+                    "ref",
+                    "pipe";
+
+      power-domains = <&gcc GCC_USB3_PHY_GDSC>;
+
+      resets = <&gcc GCC_USB3PHY_PHY_BCR>,
+               <&gcc GCC_USB3_PHY_BCR>;
+      reset-names = "phy",
+                    "common";
+
+      vdda-phy-supply = <&vreg_l4b_0p88>;
+      vdda-pll-supply = <&vreg_l1b_1p2>;
+
+      #clock-cells = <0>;
+      clock-output-names = "usb3_uni_phy_pipe_clk_src";
+
+      #phy-cells = <0>;
+    };