| Message ID | 20230905114816.2993628-2-a-verma1@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable PCIe1 on J7AHP | expand |
On 05/09/2023 13:48, Achal Verma wrote: > Added "ti,syscon-pcie-refclk-out" property to specify the ACSPCIE clock > buffer register offset in SYSCON, which would be used to enable serdes > reference clock output. > > Signed-off-by: Achal Verma <a-verma1@ti.com> > --- > .../bindings/pci/ti,j721e-pci-host.yaml | 53 +++++++++++++++++++ > 1 file changed, 53 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > index a2c5eaea57f5..27bdc52282c4 100644 > --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > @@ -44,6 +44,18 @@ properties: > - description: pcie_ctrl register offset within SYSCON > description: Specifier for configuring PCIe mode and link speed. > > + ti,syscon-pcie-refclk-out: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: Phandle to the SYSCON entry > + - description: lock2_kick0 register offset within SYSCON > + - description: lock2_kick1 register offset within SYSCON > + - description: acspcie_ctrl register offset within SYSCON > + - description: pcie_refclk_clksel register offset within SYSCON > + - description: clock source index to source ref clock > + description: Specifier for enabling ACSPCIe clock buffer for reference clock output. No, syscon is not a way to avoid creating clock/reset/power controllers. NAK. > power-domains: > maxItems: 1 > > @@ -99,6 +111,7 @@ required: > - reg > - reg-names > - ti,syscon-pcie-ctrl > + - ti,syscon-pcie-refclk-out So an ABI break? > - max-link-speed > - num-lanes > - power-domains > @@ -153,3 +166,43 @@ examples: > dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > }; > }; > + > + - > + #include <dt-bindings/mux/mux.h> > + #include <dt-bindings/mux/ti-serdes.h> > + #include <dt-bindings/phy/phy.h> > + #include <dt-bindings/phy/phy-ti.h> > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie1_rc: pcie@2910000 { > + compatible = "ti,j784s4-pcie-host"; > + reg = <0x00 0x02910000 0x00 0x1000>, No need for new example. It's anyway wrongly formatted... Best regards, Krzysztof
On Tue, 05 Sep 2023 17:18:15 +0530, Achal Verma wrote: > Added "ti,syscon-pcie-refclk-out" property to specify the ACSPCIE clock > buffer register offset in SYSCON, which would be used to enable serdes > reference clock output. > > Signed-off-by: Achal Verma <a-verma1@ti.com> > --- > .../bindings/pci/ti,j721e-pci-host.yaml | 53 +++++++++++++++++++ > 1 file changed, 53 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:171:6: [error] missing starting space in comment (comments) ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:172:6: [error] missing starting space in comment (comments) ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:173:6: [error] missing starting space in comment (comments) ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:174:6: [error] missing starting space in comment (comments) ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:177:10: [error] missing starting space in comment (comments) ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:178:10: [error] missing starting space in comment (comments) ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:180:9: [error] syntax error: expected <block end>, but found '<block mapping start>' (syntax) ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:197:18: [error] missing starting space in comment (comments) ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:198:18: [error] missing starting space in comment (comments) ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:199:17: [warning] wrong indentation: expected 8 but found 16 (indentation) dtschema/dtc warnings/errors: make[2]: *** Deleting file 'Documentation/devicetree/bindings/pci/ti,j721e-pci-host.example.dts' Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:180:9: expected <block end>, but found '<block mapping start>' make[2]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/pci/ti,j721e-pci-host.example.dts] Error 1 make[2]: *** Waiting for unfinished jobs.... Traceback (most recent call last): File "/usr/bin/yamllint", line 33, in <module> sys.exit(load_entry_point('yamllint==1.29.0', 'console_scripts', 'yamllint')()) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ File "/usr/lib/python3/dist-packages/yamllint/cli.py", line 228, in run prob_level = show_problems(problems, file, args_format=args.format, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ File "/usr/lib/python3/dist-packages/yamllint/cli.py", line 113, in show_problems for problem in problems: File "/usr/lib/python3/dist-packages/yamllint/linter.py", line 200, in _run for problem in get_cosmetic_problems(buffer, conf, filepath): File "/usr/lib/python3/dist-packages/yamllint/linter.py", line 137, in get_cosmetic_problems for problem in rule.check(rule_conf, File "/usr/lib/python3/dist-packages/yamllint/rules/indentation.py", line 583, in check yield from _check(conf, token, prev, next, nextnext, context) File "/usr/lib/python3/dist-packages/yamllint/rules/indentation.py", line 344, in _check if expected < 0: ^^^^^^^^^^^^ TypeError: '<' not supported between instances of 'NoneType' and 'int' ./Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml:180:9: expected <block end>, but found '<block mapping start>' /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml: ignoring, error parsing file make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1500: dt_binding_check] Error 2 make: *** [Makefile:234: __sub-make] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230905114816.2993628-2-a-verma1@ti.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index a2c5eaea57f5..27bdc52282c4 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -44,6 +44,18 @@ properties: - description: pcie_ctrl register offset within SYSCON description: Specifier for configuring PCIe mode and link speed. + ti,syscon-pcie-refclk-out: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: lock2_kick0 register offset within SYSCON + - description: lock2_kick1 register offset within SYSCON + - description: acspcie_ctrl register offset within SYSCON + - description: pcie_refclk_clksel register offset within SYSCON + - description: clock source index to source ref clock + description: Specifier for enabling ACSPCIe clock buffer for reference clock output. + power-domains: maxItems: 1 @@ -99,6 +111,7 @@ required: - reg - reg-names - ti,syscon-pcie-ctrl + - ti,syscon-pcie-refclk-out - max-link-speed - num-lanes - power-domains @@ -153,3 +166,43 @@ examples: dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; }; }; + + - + #include <dt-bindings/mux/mux.h> + #include <dt-bindings/mux/ti-serdes.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/phy/phy-ti.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j784s4-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-refclk-out = <&scm_conf 0x9008 0x900c 0x18090 0x8074 0x1>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 333 0>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb013>; + msi-map = <0x0 &gic_its 0x10000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + };
Added "ti,syscon-pcie-refclk-out" property to specify the ACSPCIE clock buffer register offset in SYSCON, which would be used to enable serdes reference clock output. Signed-off-by: Achal Verma <a-verma1@ti.com> --- .../bindings/pci/ti,j721e-pci-host.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+)