| Message ID | 20230904-gpll_cleanup-v1-7-de2c448f1188@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add GPLL0 as clock provider for the Qualcomm's IPQ mailbox controller | expand |
On 6.09.2023 06:56, Kathiravan Thirumoorthy wrote: > While the kernel is booting up, APSS PLL will be running at 800MHz with > GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be > configured to the rate based on the opp table and the source also will be > changed to APSS_PLL_EARLY. > > Also, dynamic scaling of CPUFreq is not supported on IPQ5332, so to switch > between the frequencies we need to park the APSS PLL in safe source, > here it is GPLL0 and then shutdown and bring up the APSS PLL in the > desired rate. So this patch is preparatory one to enable the CPUFreq on > IPQ5332. > > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > --- Please split this. Somebody reverting this in the future will have a hard time resolving conflicts. Konrad
On 9/6/2023 3:03 PM, Konrad Dybcio wrote: > On 6.09.2023 06:56, Kathiravan Thirumoorthy wrote: >> While the kernel is booting up, APSS PLL will be running at 800MHz with >> GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be >> configured to the rate based on the opp table and the source also will be >> changed to APSS_PLL_EARLY. >> >> Also, dynamic scaling of CPUFreq is not supported on IPQ5332, so to switch >> between the frequencies we need to park the APSS PLL in safe source, >> here it is GPLL0 and then shutdown and bring up the APSS PLL in the >> desired rate. So this patch is preparatory one to enable the CPUFreq on >> IPQ5332. >> >> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> >> --- > Please split this. Somebody reverting this in the future will have > a hard time resolving conflicts. Ack, will split it out in V2. > > Konrad
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db44624..82761ae199a9 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -335,8 +335,8 @@ apcs_glb: mailbox@b111000 { "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; #clock-cells = <1>; - clocks = <&a53pll>, <&xo_board>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #mbox-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 47b8b1d6730a..a30a5b893762 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -619,8 +619,8 @@ apcs_glb: mailbox@b111000 { compatible = "qcom,ipq6018-apcs-apps-global"; reg = <0x0 0x0b111000 0x0 0x1000>; #clock-cells = <1>; - clocks = <&a53pll>, <&xo>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #mbox-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 00ed71936b47..0be19267bdcf 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -719,8 +719,8 @@ apcs_glb: mailbox@b111000 { compatible = "qcom,ipq8074-apcs-apps-global", "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; - clocks = <&a53pll>, <&xo>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #clock-cells = <1>; #mbox-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 51aba071c1eb..89edb4b852df 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -652,8 +652,8 @@ apcs_glb: mailbox@b111000 { "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; #clock-cells = <1>; - clocks = <&a73pll>, <&xo_board_clk>; - clock-names = "pll", "xo"; + clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #mbox-cells = <1>; };
While the kernel is booting up, APSS PLL will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. Also, dynamic scaling of CPUFreq is not supported on IPQ5332, so to switch between the frequencies we need to park the APSS PLL in safe source, here it is GPLL0 and then shutdown and bring up the APSS PLL in the desired rate. So this patch is preparatory one to enable the CPUFreq on IPQ5332. Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-)