diff mbox series

[RFC,v3,1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property

Message ID 20230904050548.28047-2-lcherian@marvell.com (mailing list archive)
State New, archived
Headers show
Series Coresight for Kernel panic and watchdog reset | expand

Commit Message

Linu Cherian Sept. 4, 2023, 5:05 a.m. UTC
memory-region 0: Reserved trace buffer memory

  TMC ETR: When available, use this reserved memory region for
  trace data capture. Same region is used for trace data
  retention after a panic or watchdog reset.

  TMC ETF: When available, use this reserved memory region for
  trace data retention synced from internal SRAM after a panic or
  watchdog reset.

memory-region 1: Reserved meta data memory

  TMC ETR, ETF: When available, use this memory for register
  snapshot retention synced from hardware registers after a panic
  or watchdog reset.

Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
 .../devicetree/bindings/arm/arm,coresight-tmc.yaml  | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Rob Herring (Arm) Sept. 4, 2023, 6:23 a.m. UTC | #1
On Mon, 04 Sep 2023 10:35:41 +0530, Linu Cherian wrote:
> memory-region 0: Reserved trace buffer memory
> 
>   TMC ETR: When available, use this reserved memory region for
>   trace data capture. Same region is used for trace data
>   retention after a panic or watchdog reset.
> 
>   TMC ETF: When available, use this reserved memory region for
>   trace data retention synced from internal SRAM after a panic or
>   watchdog reset.
> 
> memory-region 1: Reserved meta data memory
> 
>   TMC ETR, ETF: When available, use this memory for register
>   snapshot retention synced from hardware registers after a panic
>   or watchdog reset.
> 
> Signed-off-by: Linu Cherian <lcherian@marvell.com>
> ---
>  .../devicetree/bindings/arm/arm,coresight-tmc.yaml  | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4: [error] syntax error: expected <block end>, but found '<block mapping start>' (syntax)
./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:105:5: [warning] wrong indentation: expected 5 but found 4 (indentation)

dtschema/dtc warnings/errors:
make[2]: *** Deleting file 'Documentation/devicetree/bindings/arm/arm,coresight-tmc.example.dts'
Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4: did not find expected key
make[2]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/arm/arm,coresight-tmc.example.dts] Error 1
make[2]: *** Waiting for unfinished jobs....
./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4: did not find expected key
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml: ignoring, error parsing file
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1500: dt_binding_check] Error 2
make: *** [Makefile:234: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230904050548.28047-2-lcherian@marvell.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
Suzuki K Poulose Sept. 4, 2023, 8:26 a.m. UTC | #2
On 04/09/2023 06:05, Linu Cherian wrote:
> memory-region 0: Reserved trace buffer memory
> 
>    TMC ETR: When available, use this reserved memory region for
>    trace data capture. Same region is used for trace data
>    retention after a panic or watchdog reset.
> 
>    TMC ETF: When available, use this reserved memory region for
>    trace data retention synced from internal SRAM after a panic or
>    watchdog reset.
> 
> memory-region 1: Reserved meta data memory
> 
>    TMC ETR, ETF: When available, use this memory for register
>    snapshot retention synced from hardware registers after a panic
>    or watchdog reset.

Instead of having to use a number to map the memory regions, could
we use

memory-region-names property to describe the index ? That way it
is much easier to read and is less error prone.

Names could be something like:

tmc-reserved-trace
tmc-reserved-metadata

Suzuki

> 
> Signed-off-by: Linu Cherian <lcherian@marvell.com>
> ---
>   .../devicetree/bindings/arm/arm,coresight-tmc.yaml  | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> index cb8dceaca70e..dce54978554a 100644
> --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> @@ -101,6 +101,17 @@ properties:
>             and ETF configurations.
>           $ref: /schemas/graph.yaml#/properties/port
>   
> +   memory-region:
> +    items:
> +      - description: Reserved trace buffer memory for ETR and ETF sinks.
> +        For ETR, this reserved memory region is used for trace data capture.
> +        Same region is used for trace data retention as well after a panic
> +        or watchdog reset.
> +        For ETF, this reserved memory region is used for retention of trace
> +        data synced from internal SRAM after a panic or watchdog reset.
> +
> +      - description: Reserved meta data memory. Used for ETR and ETF sinks.
> +
>   required:
>     - compatible
>     - reg
> @@ -115,6 +126,8 @@ examples:
>       etr@20070000 {
>           compatible = "arm,coresight-tmc", "arm,primecell";
>           reg = <0x20070000 0x1000>;
> +        memory-region = <&etr_trace_mem_reserved>,
> +                       <&etr_mdata_mem_reserved>;
>   
>           clocks = <&oscclk6a>;
>           clock-names = "apb_pclk";
Rob Herring (Arm) Sept. 5, 2023, 3:35 p.m. UTC | #3
On Mon, Sep 04, 2023 at 09:26:49AM +0100, Suzuki K Poulose wrote:
> On 04/09/2023 06:05, Linu Cherian wrote:
> > memory-region 0: Reserved trace buffer memory
> > 
> >    TMC ETR: When available, use this reserved memory region for
> >    trace data capture. Same region is used for trace data
> >    retention after a panic or watchdog reset.
> > 
> >    TMC ETF: When available, use this reserved memory region for
> >    trace data retention synced from internal SRAM after a panic or
> >    watchdog reset.
> > 
> > memory-region 1: Reserved meta data memory
> > 
> >    TMC ETR, ETF: When available, use this memory for register
> >    snapshot retention synced from hardware registers after a panic
> >    or watchdog reset.
> 
> Instead of having to use a number to map the memory regions, could
> we use
> 
> memory-region-names property to describe the index ? That way it
> is much easier to read and is less error prone.

You can, but the order should still be defined.

> Names could be something like:
> 
> tmc-reserved-trace
> tmc-reserved-metadata

Names are local to the binding. So 'tmc' is redundant. And everything is 
a reserved region for 'memory-region', so that's redundant too.

Rob
Linu Cherian Sept. 9, 2023, 2:06 p.m. UTC | #4
Hi Suzuki,

> -----Original Message-----
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> Sent: Monday, September 4, 2023 1:57 PM
> To: Linu Cherian <lcherian@marvell.com>; mike.leach@linaro.org;
> james.clark@arm.com; leo.yan@linaro.org
> Cc: linux-arm-kernel@lists.infradead.org; coresight@lists.linaro.org; linux-
> kernel@vger.kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> devicetree@vger.kernel.org; Sunil Kovvuri Goutham
> <sgoutham@marvell.com>; George Cherian <gcherian@marvell.com>
> Subject: [EXT] Re: [RFC PATCH v3 1/7] dt-bindings: arm: coresight-tmc: Add
> "memory-region" property
> 
> External Email
> 
> ----------------------------------------------------------------------
> On 04/09/2023 06:05, Linu Cherian wrote:
> > memory-region 0: Reserved trace buffer memory
> >
> >    TMC ETR: When available, use this reserved memory region for
> >    trace data capture. Same region is used for trace data
> >    retention after a panic or watchdog reset.
> >
> >    TMC ETF: When available, use this reserved memory region for
> >    trace data retention synced from internal SRAM after a panic or
> >    watchdog reset.
> >
> > memory-region 1: Reserved meta data memory
> >
> >    TMC ETR, ETF: When available, use this memory for register
> >    snapshot retention synced from hardware registers after a panic
> >    or watchdog reset.
> 
> Instead of having to use a number to map the memory regions, could we use
> 
> memory-region-names property to describe the index ? That way it is much
> easier to read and is less error prone.
> 
> Names could be something like:
> 
> tmc-reserved-trace
> tmc-reserved-metadata
> 

Ack. Will use names in the next version. Will take care of the suggestions from Rob.

> Suzuki
> 
> >
> > Signed-off-by: Linu Cherian <lcherian@marvell.com>
> > ---
> >   .../devicetree/bindings/arm/arm,coresight-tmc.yaml  | 13
> +++++++++++++
> >   1 file changed, 13 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> > b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> > index cb8dceaca70e..dce54978554a 100644
> > --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> > @@ -101,6 +101,17 @@ properties:
> >             and ETF configurations.
> >           $ref: /schemas/graph.yaml#/properties/port
> >
> > +   memory-region:
> > +    items:
> > +      - description: Reserved trace buffer memory for ETR and ETF sinks.
> > +        For ETR, this reserved memory region is used for trace data capture.
> > +        Same region is used for trace data retention as well after a panic
> > +        or watchdog reset.
> > +        For ETF, this reserved memory region is used for retention of trace
> > +        data synced from internal SRAM after a panic or watchdog reset.
> > +
> > +      - description: Reserved meta data memory. Used for ETR and ETF sinks.
> > +
> >   required:
> >     - compatible
> >     - reg
> > @@ -115,6 +126,8 @@ examples:
> >       etr@20070000 {
> >           compatible = "arm,coresight-tmc", "arm,primecell";
> >           reg = <0x20070000 0x1000>;
> > +        memory-region = <&etr_trace_mem_reserved>,
> > +                       <&etr_mdata_mem_reserved>;
> >
> >           clocks = <&oscclk6a>;
> >           clock-names = "apb_pclk";
Linu Cherian Sept. 9, 2023, 2:12 p.m. UTC | #5
Hi Rob,

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Monday, September 4, 2023 11:53 AM
> To: Linu Cherian <lcherian@marvell.com>
> Cc: linux-arm-kernel@lists.infradead.org; mike.leach@linaro.org; Sunil
> Kovvuri Goutham <sgoutham@marvell.com>; james.clark@arm.com;
> leo.yan@linaro.org; linux-kernel@vger.kernel.org;
> krzysztof.kozlowski+dt@linaro.org; George Cherian
> <gcherian@marvell.com>; suzuki.poulose@arm.com;
> coresight@lists.linaro.org; devicetree@vger.kernel.org;
> conor+dt@kernel.org; robh+dt@kernel.org
> Subject: [EXT] Re: [RFC PATCH v3 1/7] dt-bindings: arm: coresight-tmc: Add
> "memory-region" property
> 
> External Email
> 
> ----------------------------------------------------------------------
> 
> On Mon, 04 Sep 2023 10:35:41 +0530, Linu Cherian wrote:
> > memory-region 0: Reserved trace buffer memory
> >
> >   TMC ETR: When available, use this reserved memory region for
> >   trace data capture. Same region is used for trace data
> >   retention after a panic or watchdog reset.
> >
> >   TMC ETF: When available, use this reserved memory region for
> >   trace data retention synced from internal SRAM after a panic or
> >   watchdog reset.
> >
> > memory-region 1: Reserved meta data memory
> >
> >   TMC ETR, ETF: When available, use this memory for register
> >   snapshot retention synced from hardware registers after a panic
> >   or watchdog reset.
> >
> > Signed-off-by: Linu Cherian <lcherian@marvell.com>
> > ---
> >  .../devicetree/bindings/arm/arm,coresight-tmc.yaml  | 13
> > +++++++++++++
> >  1 file changed, 13 insertions(+)
> >
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m
> dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4:
> [error] syntax error: expected <block end>, but found '<block mapping
> start>' (syntax)
> ./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:105:5:
> [warning] wrong indentation: expected 5 but found 4 (indentation)
> 
> dtschema/dtc warnings/errors:
> make[2]: *** Deleting file
> 'Documentation/devicetree/bindings/arm/arm,coresight-tmc.example.dts'
> Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4: did
> not find expected key
> make[2]: *** [Documentation/devicetree/bindings/Makefile:26:
> Documentation/devicetree/bindings/arm/arm,coresight-tmc.example.dts]
> Error 1
> make[2]: *** Waiting for unfinished jobs....
> ./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4:
> did not find expected key
> /builds/robherring/dt-review-
> ci/linux/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:
> ignoring, error parsing file
> make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1500:
> dt_binding_check] Error 2
> make: *** [Makefile:234: __sub-make] Error 2
> 
> doc reference errors (make refcheckdocs):
> 
> See https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__patchwork.ozlabs.org_project_devicetree-
> 2Dbindings_patch_20230904050548.28047-2D2-2Dlcherian-
> 40marvell.com&d=DwIDaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=DI9kird_6lFtBC
> VoGa5ogk3dJwsUlHLjLlgu0r46iU4&m=_ay-
> WtrQlhIwxRafvVeVQHuS8jVWvIzZWMmn3Kp2yAVpxITz-
> rjWiL4cMybMomHi&s=zvUJitULz2sVzal1I78gUQ3sBBTSAZmwDziKSNJbxwM&
> e=
> 
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
> 
> If you already ran 'make dt_binding_check' and didn't see the above error(s),
> then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your
> schema.

Ack. Will fix this in next version.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
index cb8dceaca70e..dce54978554a 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
@@ -101,6 +101,17 @@  properties:
           and ETF configurations.
         $ref: /schemas/graph.yaml#/properties/port
 
+   memory-region:
+    items:
+      - description: Reserved trace buffer memory for ETR and ETF sinks.
+        For ETR, this reserved memory region is used for trace data capture.
+        Same region is used for trace data retention as well after a panic
+        or watchdog reset.
+        For ETF, this reserved memory region is used for retention of trace
+        data synced from internal SRAM after a panic or watchdog reset.
+
+      - description: Reserved meta data memory. Used for ETR and ETF sinks.
+
 required:
   - compatible
   - reg
@@ -115,6 +126,8 @@  examples:
     etr@20070000 {
         compatible = "arm,coresight-tmc", "arm,primecell";
         reg = <0x20070000 0x1000>;
+        memory-region = <&etr_trace_mem_reserved>,
+                       <&etr_mdata_mem_reserved>;
 
         clocks = <&oscclk6a>;
         clock-names = "apb_pclk";