| Message ID | 20230904-gpll_cleanup-v1-6-de2c448f1188@quicinc.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | Add GPLL0 as clock provider for the Qualcomm's IPQ mailbox controller | expand |
On 06. 09. 2023. 06:56, Kathiravan Thirumoorthy wrote: > While the kernel is booting up, APSS PLL will be running at 800MHz with > GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be > configured and select the rate based on the opp table and the source will > be changed to APSS_PLL_EARLY. > > Without this patch, CPU Freq driver reports that CPU is running at 24MHz > instead of the 800MHz. > > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> I can confirm that this works on IPQ8074 as well, it now properly sees the default CPU clock of 800MHz instead of XO rate. Tested-by: Robert Marko <robimarko@gmail.com> > --- > drivers/clk/qcom/apss-ipq6018.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c > index f2f502e2d5a4..4e13a085a857 100644 > --- a/drivers/clk/qcom/apss-ipq6018.c > +++ b/drivers/clk/qcom/apss-ipq6018.c > @@ -20,16 +20,19 @@ > > enum { > P_XO, > + P_GPLL0, > P_APSS_PLL_EARLY, > }; > > static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { > { .fw_name = "xo" }, > + { .fw_name = "gpll0" }, > { .fw_name = "pll" }, > }; > > static const struct parent_map parents_apcs_alias0_clk_src_map[] = { > { P_XO, 0 }, > + { P_GPLL0, 4 }, > { P_APSS_PLL_EARLY, 5 }, > }; > >
On 6.09.2023 06:56, Kathiravan Thirumoorthy wrote: > While the kernel is booting up, APSS PLL will be running at 800MHz with > GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be > configured and select the rate based on the opp table and the source will > be changed to APSS_PLL_EARLY. > > Without this patch, CPU Freq driver reports that CPU is running at 24MHz > instead of the 800MHz. > > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c index f2f502e2d5a4..4e13a085a857 100644 --- a/drivers/clk/qcom/apss-ipq6018.c +++ b/drivers/clk/qcom/apss-ipq6018.c @@ -20,16 +20,19 @@ enum { P_XO, + P_GPLL0, P_APSS_PLL_EARLY, }; static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { { .fw_name = "xo" }, + { .fw_name = "gpll0" }, { .fw_name = "pll" }, }; static const struct parent_map parents_apcs_alias0_clk_src_map[] = { { P_XO, 0 }, + { P_GPLL0, 4 }, { P_APSS_PLL_EARLY, 5 }, };
While the kernel is booting up, APSS PLL will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured and select the rate based on the opp table and the source will be changed to APSS_PLL_EARLY. Without this patch, CPU Freq driver reports that CPU is running at 24MHz instead of the 800MHz. Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> --- drivers/clk/qcom/apss-ipq6018.c | 3 +++ 1 file changed, 3 insertions(+)