| Message ID | 20230904132806.6094-5-Jonathan.Cameron@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/cxl: Minor CXL emulation fixes and cleanup | expand |
On 4/9/23 15:28, Jonathan Cameron wrote: > From: Li Zhijian <lizhijian@cn.fujitsu.com> > > Using the same style as elsewhere for topology / topo > > Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com> > Link: https://lore.kernel.org/r/20230519085802.2106900-2-lizhijian@cn.fujitsu.com > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > docs/system/devices/cxl.rst | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On Mon, Sep 04, 2023 at 02:28:06PM +0100, Jonathan Cameron wrote: > From: Li Zhijian <lizhijian@cn.fujitsu.com> > > Using the same style as elsewhere for topology / topo > > Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com> > Link: https://urldefense.com/v3/__https://lore.kernel.org/r/20230519085802.2106900-2-lizhijian@cn.fujitsu.com__;!!EwVzqGoTKBqv-0DWAJBm!TWHVrdL5Ys7OOFU_w1CJQ5DC6mxu649kYA9GYDJ182CNPuQqpVkWYsB5mlJpVd_BAAmhxCD4Si2CkMERZI7ZE03kPz2c$ > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- Reviewed-by: Fan Ni <fan.ni@samsung.com> > docs/system/devices/cxl.rst | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst > index f12011e230..b742120657 100644 > --- a/docs/system/devices/cxl.rst > +++ b/docs/system/devices/cxl.rst > @@ -157,7 +157,7 @@ responsible for allocating appropriate ranges from within the CFMWs > and exposing those via normal memory configurations as would be done > for system RAM. > > -Example system Topology. x marks the match in each decoder level:: > +Example system topology. x marks the match in each decoder level:: > > |<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->| > | __________ __________________________________ __________ | > @@ -187,8 +187,8 @@ Example system Topology. x marks the match in each decoder level:: > ___________|___ __________|__ __|_________ ___|_________ > (3)| Root Port 0 | | Root Port 1 | | Root Port 2| | Root Port 3 | > | Appears in | | Appears in | | Appears in | | Appear in | > - | PCI topology | | PCI Topology| | PCI Topo | | PCI Topo | > - | As 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 | > + | PCI topology | | PCI topology| | PCI topo | | PCI topo | > + | as 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 | > |_______________| |_____________| |____________| |_____________| > | | | | > | | | | > @@ -272,7 +272,7 @@ Example topology involving a switch:: > | Root Port 0 | > | Appears in | > | PCI topology | > - | As 0c:00.0 | > + | as 0c:00.0 | > |___________x___| > | > | > -- > 2.39.2 >
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f12011e230..b742120657 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -157,7 +157,7 @@ responsible for allocating appropriate ranges from within the CFMWs and exposing those via normal memory configurations as would be done for system RAM. -Example system Topology. x marks the match in each decoder level:: +Example system topology. x marks the match in each decoder level:: |<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->| | __________ __________________________________ __________ | @@ -187,8 +187,8 @@ Example system Topology. x marks the match in each decoder level:: ___________|___ __________|__ __|_________ ___|_________ (3)| Root Port 0 | | Root Port 1 | | Root Port 2| | Root Port 3 | | Appears in | | Appears in | | Appears in | | Appear in | - | PCI topology | | PCI Topology| | PCI Topo | | PCI Topo | - | As 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 | + | PCI topology | | PCI topology| | PCI topo | | PCI topo | + | as 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 | |_______________| |_____________| |____________| |_____________| | | | | | | | | @@ -272,7 +272,7 @@ Example topology involving a switch:: | Root Port 0 | | Appears in | | PCI topology | - | As 0c:00.0 | + | as 0c:00.0 | |___________x___| | |