| Message ID | 20230822024155.26670-4-shuijing.li@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add compatible to increase MT8188 audio control | expand |
Hi, Shuijing: On Tue, 2023-08-22 at 10:41 +0800, Shuijing Li wrote: > Due to the difference of HW, different dividers need to be set. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Shuijing Li <shuijing.li@mediatek.com> > --- > Changes in v6: > Move MT8188 defintion to patch[4/4]. > per suggestion from the previous thread: > https://lore.kernel.org/all/60ba1ab40fc943f1abf3e78b0b32223be402302c.camel@mediatek.com/ > Changes in v4: > list all configuration for MT8188 and MT8195. > per suggestion from the previous thread: > https://lore.kernel.org/all/a9d1b9b7ef4780f51574d0bbbe28f6dd109a6ab8.camel@mediatek.com/ > Changes in v3: > Separate these two things into two different patches. > per suggestion from the previous thread: > https://lore.kernel.org/lkml/e2ad22bcba31797f38a12a488d4246a01bf0cb2e.camel@mediatek.com/ > Changes in v2: > - change the variables' name to be more descriptive > - add a comment that describes the function of > mtk_dp_audio_sample_arrange > - reduce indentation by doing the inverse check > - add a definition of some bits > - add support for mediatek, mt8188-edp-tx > per suggestion from the previous thread: > https://lore.kernel.org/lkml/ac0fcec9-a2fe-06cc-c727-189ef7babe9c@collabora.com/ > --- > drivers/gpu/drm/mediatek/mtk_dp.c | 5 ++++- > drivers/gpu/drm/mediatek/mtk_dp_reg.h | 12 ++++++------ > 2 files changed, 10 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c > b/drivers/gpu/drm/mediatek/mtk_dp.c > index badb205ffff2..0ba9a4fdf839 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dp.c > +++ b/drivers/gpu/drm/mediatek/mtk_dp.c > @@ -140,6 +140,7 @@ struct mtk_dp_data { > const struct mtk_dp_efuse_fmt *efuse_fmt; > bool audio_supported; > bool audio_pkt_in_hblank_area; > + u16 audio_m_div2_bit; > }; > > static const struct mtk_dp_efuse_fmt > mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = { > @@ -648,7 +649,7 @@ static void > mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp, > static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp) > { > mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, > - AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, > + mtk_dp->data->audio_m_div2_bit, > AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK); > } > > @@ -2635,6 +2636,7 @@ static const struct mtk_dp_data mt8195_edp_data > = { > .smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, > .efuse_fmt = mt8195_edp_efuse_fmt, > .audio_supported = false, > + .audio_m_div2_bit = > MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, > }; > > static const struct mtk_dp_data mt8195_dp_data = { > @@ -2642,6 +2644,7 @@ static const struct mtk_dp_data mt8195_dp_data > = { > .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE, > .efuse_fmt = mt8195_dp_efuse_fmt, > .audio_supported = true, > + .audio_m_div2_bit = > MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, > }; > > static const struct of_device_id mtk_dp_of_match[] = { > diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h > b/drivers/gpu/drm/mediatek/mtk_dp_reg.h > index f38d6ff12afe..b9859ef067ce 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h > +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h > @@ -159,12 +159,12 @@ > #define MTK_DP_ENC0_P0_30BC 0x30bc > #define ISRC_CONT_DP_ENC0_P0 BIT(0) > #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8) > -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8) > -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8) > -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8) > -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8) > -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8) > -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8) > +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << > 8) > +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << > 8) > +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << > 8) > +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << > 8) > +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << > 8) > +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << > 8) > #define MTK_DP_ENC0_P0_30D8 0x30d8 > #define MTK_DP_ENC0_P0_312C 0x312c > #define ASP_HB2_DP_ENC0_P0_MASK GENMASK > (7, 0)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index badb205ffff2..0ba9a4fdf839 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -140,6 +140,7 @@ struct mtk_dp_data { const struct mtk_dp_efuse_fmt *efuse_fmt; bool audio_supported; bool audio_pkt_in_hblank_area; + u16 audio_m_div2_bit; }; static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = { @@ -648,7 +649,7 @@ static void mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp, static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp) { mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, - AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, + mtk_dp->data->audio_m_div2_bit, AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK); } @@ -2635,6 +2636,7 @@ static const struct mtk_dp_data mt8195_edp_data = { .smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, .efuse_fmt = mt8195_edp_efuse_fmt, .audio_supported = false, + .audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; static const struct mtk_dp_data mt8195_dp_data = { @@ -2642,6 +2644,7 @@ static const struct mtk_dp_data mt8195_dp_data = { .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE, .efuse_fmt = mt8195_dp_efuse_fmt, .audio_supported = true, + .audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; static const struct of_device_id mtk_dp_of_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h index f38d6ff12afe..b9859ef067ce 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -159,12 +159,12 @@ #define MTK_DP_ENC0_P0_30BC 0x30bc #define ISRC_CONT_DP_ENC0_P0 BIT(0) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8) #define MTK_DP_ENC0_P0_30D8 0x30d8 #define MTK_DP_ENC0_P0_312C 0x312c #define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0)
Due to the difference of HW, different dividers need to be set. Signed-off-by: Shuijing Li <shuijing.li@mediatek.com> --- Changes in v6: Move MT8188 defintion to patch[4/4]. per suggestion from the previous thread: https://lore.kernel.org/all/60ba1ab40fc943f1abf3e78b0b32223be402302c.camel@mediatek.com/ Changes in v4: list all configuration for MT8188 and MT8195. per suggestion from the previous thread: https://lore.kernel.org/all/a9d1b9b7ef4780f51574d0bbbe28f6dd109a6ab8.camel@mediatek.com/ Changes in v3: Separate these two things into two different patches. per suggestion from the previous thread: https://lore.kernel.org/lkml/e2ad22bcba31797f38a12a488d4246a01bf0cb2e.camel@mediatek.com/ Changes in v2: - change the variables' name to be more descriptive - add a comment that describes the function of mtk_dp_audio_sample_arrange - reduce indentation by doing the inverse check - add a definition of some bits - add support for mediatek, mt8188-edp-tx per suggestion from the previous thread: https://lore.kernel.org/lkml/ac0fcec9-a2fe-06cc-c727-189ef7babe9c@collabora.com/ --- drivers/gpu/drm/mediatek/mtk_dp.c | 5 ++++- drivers/gpu/drm/mediatek/mtk_dp_reg.h | 12 ++++++------ 2 files changed, 10 insertions(+), 7 deletions(-)