| Message ID | 20230917095832.39007-1-marek.vasut+renesas@mailbox.org (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: renesas: r8a7795: Constify r8a7795_*_clks | expand |
Hi Marek, Thanks for your patch! On Sun, Sep 17, 2023 at 11:58 AM Marek Vasut <marek.vasut+renesas@mailbox.org> wrote: > Make r8a7795_core_clks and r8a7795_mod_clks arrays const and align them > with the other clock tables in other *cpg-mssr.c . No functional change. > > Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Indeed, these are no longer modified since commit b1dec4e78599a2ce ("clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*"). Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v6.7. > --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c > @@ -51,7 +51,7 @@ enum clk_ids { > MOD_CLK_BASE > }; > > -static struct cpg_core_clk r8a7795_core_clks[] __initdata = { > +static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { > /* External Clock Inputs */ > DEF_INPUT("extal", CLK_EXTAL), > DEF_INPUT("extalr", CLK_EXTALR), > @@ -128,7 +128,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { > DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), > }; > > -static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { > +static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { > DEF_MOD("3dge", 112, R8A7795_CLK_ZG), > DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), > DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index ad20b3301ef6..e47d9b1fcc0a 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -51,7 +51,7 @@ enum clk_ids { MOD_CLK_BASE }; -static struct cpg_core_clk r8a7795_core_clks[] __initdata = { +static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), @@ -128,7 +128,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; -static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { +static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("3dge", 112, R8A7795_CLK_ZG), DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
Make r8a7795_core_clks and r8a7795_mod_clks arrays const and align them with the other clock tables in other *cpg-mssr.c . No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> --- Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)