| Message ID | 20230913-gpll_cleanup-v2-8-c8ceb1a37680@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add GPLL0 as clock provider for the Qualcomm's IPQ mailbox controller | expand |
On 14.09.2023 08:59, Kathiravan Thirumoorthy wrote: > While the kernel is booting up, APSS PLL will be running at 800MHz with > GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be > configured to the rate based on the opp table and the source also will > be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, > with this inclusion, CPU Freq correctly reports that CPU is running at > 800MHz rather than 24MHz. > > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On 9/27/2023 5:03 PM, Konrad Dybcio wrote: > On 14.09.2023 08:59, Kathiravan Thirumoorthy wrote: >> While the kernel is booting up, APSS PLL will be running at 800MHz with >> GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be >> configured to the rate based on the opp table and the source also will >> be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, >> with this inclusion, CPU Freq correctly reports that CPU is running at >> 800MHz rather than 24MHz. >> >> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> >> --- > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > Konrad Thanks Konrad. I just realized that, in commit message, the statement "APSS PLL will be running at 800MHz" should be "APSS clock / CPU clock will be running at 800MHz". Bjorn, will you be able to fix it up while applying (all 4 DTS changes needs update) or shall I respin it? Thanks, Kathiravan T.
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 00ed71936b47..0be19267bdcf 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -719,8 +719,8 @@ apcs_glb: mailbox@b111000 { compatible = "qcom,ipq8074-apcs-apps-global", "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; - clocks = <&a53pll>, <&xo>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #clock-cells = <1>; #mbox-cells = <1>;
While the kernel is booting up, APSS PLL will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> --- Changes in V2: - Splitted the change into target specific file --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)