| Message ID | 20231004220739.1313307-1-jonathan.cavitt@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Subject: [PATCH dii-client v6 0/4] drm/i915: Define and use GuC and CTB TLB invalidation routines | expand |
Hi Jonathan, > CI changes > > Possible regressions > > • boot: > □ bat-dg1-5: PASS -> FAIL > > IGT changes > > Possible regressions > > • igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling: > > □ bat-adlm-1: PASS -> INCOMPLETE > • igt@kms_busy@basic@flip: > > □ bat-adlp-11: PASS -> ABORT > > □ bat-adlp-6: PASS -> INCOMPLETE > > • igt@kms_busy@basic@modeset: > > □ bat-adlp-11: PASS -> DMESG-WARN > • igt@kms_force_connector_basic@force-connector-state: > > □ bat-rpls-1: PASS -> INCOMPLETE Although these failures appear very consistently, they don't look related to your patch. But still I wonder why they show up so consistently. Is anyone from the list able to provide some thoughts? Andi
Hi, > > CI changes > > > > Possible regressions > > > > • boot: > > □ bat-dg1-5: PASS -> FAIL > > > > IGT changes > > > > Possible regressions > > > > • igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling: > > > > □ bat-adlm-1: PASS -> INCOMPLETE > > • igt@kms_busy@basic@flip: > > > > □ bat-adlp-11: PASS -> ABORT > > > > □ bat-adlp-6: PASS -> INCOMPLETE > > > > • igt@kms_busy@basic@modeset: > > > > □ bat-adlp-11: PASS -> DMESG-WARN > > • igt@kms_force_connector_basic@force-connector-state: > > > > □ bat-rpls-1: PASS -> INCOMPLETE > > Although these failures appear very consistently, they don't look > related to your patch. But still I wonder why they show up so > consistently. > > Is anyone from the list able to provide some thoughts? Please, ignore, they go through guc_ggtt_invalidate... the log was hidden :-) Andi
The GuC firmware had defined the interface for Translation Look-Aside Buffer (TLB) invalidation. We should use this interface when invalidating the engine and GuC TLBs. Add additional functionality to intel_gt_invalidate_tlb, invalidating the GuC TLBs and falling back to GT invalidation when the GuC is disabled. The invalidation is done by sending a request directly to the GuC tlb_lookup that invalidates the table. The invalidation is submitted as a wait request and is performed in the CT event handler. This means we cannot perform this TLB invalidation path if the CT is not enabled. If the request isn't fulfilled in two seconds, this would constitute an error in the invalidation as that would constitute either a lost request or a severe GuC overload. The tlb_lookup table is allocated as an xarray because the set of pending TLB invalidations may have no upper bound. The consequence of this is that all actions interfacting with this table need to use the xarray functions, such as xa_alloc_cyclic_irq for array insertion. With this new invalidation routine, we can perform GuC-based GGTT invalidations. GuC-based GGTT invalidation is incompatible with MMIO invalidation so we should not perform MMIO invalidation when GuC-based GGTT invalidation is expected. v2: - Add missing supporting patches. v3: - Split suspend/resume changes and multi-gt support into separate patches. - Only perform GuC TLB invalidation functions when supported. - Move intel_guc_is_enabled check function to usage location. - Address comments. v4: - Change conditions for GuC-based tlb invalidation support to a pci tag that's only active for MTL. - Address some FIXMEs and formatting issues. - Move suspend/resume changes to helper functions in intel_gt.h - Improve comment for ct_handle_event change. - Use cleaner if-else conditions. - Address comments. v5: - Reintroduce missing change to selftest msleep duration - Move suspend/resume loops from intel_gt.h to intel_tlb.c, making them no longer static inlines. - Remove superfluous blocking and error checks. - Move ct_handle_event exception to general case in ct_process_request. - Explain usage of xa_alloc_cyclic_irq. - Modify explanation of purpose of OUTSTANDING_GUC_TIMEOUT_PERIOD macro. - Explain purpose of performing tlb invalidation twice in intel_gt_tlb_resume_all. v6: - Add this cover letter. - Fix explanation of purpose of OUTSTANDING_GUC_TIMEOUT_PERIOD macro again. - s/pci tags/pci flags - Enable GuC TLB Invalidations separately from adding the flags to do so. Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> CC: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> CC: Bruce Chang <yu.bruce.chang@intel.com> CC: Chris Wilson <chris.p.wilson@intel.com> CC: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> CC: Aravind Iddamsetty <aravind.iddamsetty@intel.com> CC: Fei Yang <fei.yang@intel.com> CC: Andi Shyti <andi.shyti@linux.intel.com> CC: John Harrison <john.c.harrison@intel.com> CC: Nirmoy Das <nirmoy.das@intel.com> CC: Janusz Krzysztofik <janusz.krzysztofik@intel.com> CC: Matt Roper <matthew.d.roper@intel.com> CC: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Jonathan Cavitt (4): drm/i915: Add GuC TLB Invalidation pci flags drm/i915: No TLB invalidation on wedged or suspended GT drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck drm/i915: Enable GuC TLB invalidations for MTL Prathap Kumar Valsan (1): drm/i915: Define and use GuC and CTB TLB invalidation routines drivers/gpu/drm/i915/gt/intel_ggtt.c | 42 +++- drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/gt/intel_tlb.c | 39 ++- drivers/gpu/drm/i915/gt/intel_tlb.h | 3 + drivers/gpu/drm/i915/gt/selftest_tlb.c | 2 +- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 33 +++ drivers/gpu/drm/i915/gt/uc/intel_guc.h | 23 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 + drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 236 +++++++++++++++++- drivers/gpu/drm/i915/i915_driver.c | 6 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 3 +- 14 files changed, 379 insertions(+), 18 deletions(-)