| Message ID | 20230928113629.103188-3-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3,1/8] drm: lcdif: improve burst size configuration comment | expand |
On Thursday, September 28, 2023 7:36 PM, Lucas Stach <l.stach@pengutronix.de> wrote: > Otherwise the DMA enable races with the fetch start, which causes > wrong or no data to be scanned out on the first frame. Also there > is no point in waiting for the DMA disable when the controller is > going to shut down. Simply disable the display first so no further > fetches are triggered and then shut down DMA. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > v3: new patch > --- > drivers/gpu/drm/mxsfb/lcdif_kms.c | 23 ++++++++--------------- > 1 file changed, 8 insertions(+), 15 deletions(-) It seems that this one is the key to make fb pixel format change work ok for i.MX8mp LCDIF with modetest. However, there is about 20% probability to show constant color with the same test running on i.MX93 LCDIF. On top of this patch series, duplicating plane update in crtc atomic_enable like downstream driver does seems avoid the issue for i.MX93. Regards, Liu Ying
diff --git a/drivers/gpu/drm/mxsfb/lcdif_kms.c b/drivers/gpu/drm/mxsfb/lcdif_kms.c index e277592e5fa5..6a292f4b332b 100644 --- a/drivers/gpu/drm/mxsfb/lcdif_kms.c +++ b/drivers/gpu/drm/mxsfb/lcdif_kms.c @@ -358,34 +358,27 @@ static void lcdif_enable_controller(struct lcdif_drm_private *lcdif) writel(INT_ENABLE_D1_PLANE_PANIC_EN, lcdif->base + LCDC_V8_INT_ENABLE_D1); - reg = readl(lcdif->base + LCDC_V8_DISP_PARA); - reg |= DISP_PARA_DISP_ON; - writel(reg, lcdif->base + LCDC_V8_DISP_PARA); - reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5); reg |= CTRLDESCL0_5_EN; writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5); + + reg = readl(lcdif->base + LCDC_V8_DISP_PARA); + reg |= DISP_PARA_DISP_ON; + writel(reg, lcdif->base + LCDC_V8_DISP_PARA); } static void lcdif_disable_controller(struct lcdif_drm_private *lcdif) { u32 reg; - int ret; - - reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5); - reg &= ~CTRLDESCL0_5_EN; - writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5); - - ret = readl_poll_timeout(lcdif->base + LCDC_V8_CTRLDESCL0_5, - reg, !(reg & CTRLDESCL0_5_EN), - 0, 36000); /* Wait ~2 frame times max */ - if (ret) - drm_err(lcdif->drm, "Failed to disable controller!\n"); reg = readl(lcdif->base + LCDC_V8_DISP_PARA); reg &= ~DISP_PARA_DISP_ON; writel(reg, lcdif->base + LCDC_V8_DISP_PARA); + reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5); + reg &= ~CTRLDESCL0_5_EN; + writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5); + /* Disable FIFO Panic NoC priority booster. */ writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D1); }
Otherwise the DMA enable races with the fetch start, which causes wrong or no data to be scanned out on the first frame. Also there is no point in waiting for the DMA disable when the controller is going to shut down. Simply disable the display first so no further fetches are triggered and then shut down DMA. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- v3: new patch --- drivers/gpu/drm/mxsfb/lcdif_kms.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-)