| Message ID | 20231009-smog-gag-3ba67e68126b@wendy (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 06e6897afc563945abc21bcd8840dce7ed4e3927 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | riscv,isa-extensions additions | expand |
Hi Conor, On Mon, Oct 9, 2023 at 11:44 AM Conor Dooley <conor.dooley@microchip.com> wrote: > Convert the RZ/Five devicetrees to use the new properties > "riscv,isa-base" & "riscv,isa-extensions". > For compatibility with other projects, "riscv,isa" remains. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Thanks for your patch! > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > @@ -24,6 +24,9 @@ cpu0: cpu@0 { > reg = <0x0>; > status = "okay"; > riscv,isa = "rv64imafdc"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > + "zifencei", "zihpm"; LGMT, so Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> I could not review the "zi*" parts, as the documentation that I have does not mention these. > mmu-type = "riscv,sv39"; > i-cache-size = <0x8000>; > i-cache-line-size = <0x40>; Gr{oetje,eeting}s, Geert
On Mon, Oct 09, 2023 at 02:15:47PM +0200, Geert Uytterhoeven wrote: > Hi Conor, > > On Mon, Oct 9, 2023 at 11:44 AM Conor Dooley <conor.dooley@microchip.com> wrote: > > Convert the RZ/Five devicetrees to use the new properties > > "riscv,isa-base" & "riscv,isa-extensions". > > For compatibility with other projects, "riscv,isa" remains. > > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > Thanks for your patch! > > > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > @@ -24,6 +24,9 @@ cpu0: cpu@0 { > > reg = <0x0>; > > status = "okay"; > > riscv,isa = "rv64imafdc"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > > + "zifencei", "zihpm"; > > LGMT, so > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > I could not review the "zi*" parts, as the documentation that I have > does not mention these. These are effectively the assumptions that the kernel already makes, for things that used to be part of the base isa (or were assumed to be) that are now extensions in their own right. The Zihpm it'd be good if someone from the Renesas or Andes sides could confirm though. Cheers, Conor. > > > mmu-type = "riscv,sv39"; > > i-cache-size = <0x8000>; > > i-cache-line-size = <0x40>; > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
On Mon, Oct 09, 2023 at 10:37:48AM +0100, Conor Dooley wrote: > Convert the RZ/Five devicetrees to use the new properties > "riscv,isa-base" & "riscv,isa-extensions". > For compatibility with other projects, "riscv,isa" remains. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > index b0796015e36b..eb301d8eb2b0 100644 > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > @@ -24,6 +24,9 @@ cpu0: cpu@0 { > reg = <0x0>; > status = "okay"; > riscv,isa = "rv64imafdc"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > + "zifencei", "zihpm"; We do have zihpm, and OpenSBI can also probe its existence. Boot HART ISA Extensions : zihpm Boot HART MHPM Info : 4 (0x00000078) By the way, we will append "xandespmu" here. I hope this is an appropriate way to add a new custom extension. > mmu-type = "riscv,sv39"; > i-cache-size = <0x8000>; > i-cache-line-size = <0x40>;
Hi Yu-Chien, On Mon, Oct 16, 2023 at 8:10 AM Yu-Chien Peter Lin <peterlin@andestech.com> wrote: > On Mon, Oct 09, 2023 at 10:37:48AM +0100, Conor Dooley wrote: > > Convert the RZ/Five devicetrees to use the new properties > > "riscv,isa-base" & "riscv,isa-extensions". > > For compatibility with other projects, "riscv,isa" remains. > > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > index b0796015e36b..eb301d8eb2b0 100644 > > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > @@ -24,6 +24,9 @@ cpu0: cpu@0 { > > reg = <0x0>; > > status = "okay"; > > riscv,isa = "rv64imafdc"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > > + "zifencei", "zihpm"; > > We do have zihpm, and OpenSBI can also probe its existence. > > Boot HART ISA Extensions : zihpm > Boot HART MHPM Info : 4 (0x00000078) Thank you, I hadn't digested the full output from OpenSBI yet, and I can confirm this is present in that output. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index b0796015e36b..eb301d8eb2b0 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -24,6 +24,9 @@ cpu0: cpu@0 { reg = <0x0>; status = "okay"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>;
Convert the RZ/Five devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++ 1 file changed, 3 insertions(+)