| Message ID | 20231011000248.2181018-8-jonathan.cavitt@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Define and use GuC and CTB TLB invalidation routines | expand |
On 10/11/2023 2:02 AM, Jonathan Cavitt wrote: > Enable GuC TLB invalidations for MTL. Though more platforms than just > MTL support GuC TLB invalidations, MTL is presently the only platform > that requires it for any purpose, so only enable it there for now to > minimize cross-platform impact. > > Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> With a happy CI this is Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> > --- > drivers/gpu/drm/i915/i915_pci.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index df7c261410f79..d4b51ececbb12 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -829,6 +829,7 @@ static const struct intel_device_info mtl_info = { > .has_flat_ccs = 0, > .has_gmd_id = 1, > .has_guc_deprivilege = 1, > + .has_guc_tlb_invalidation = 1, > .has_llc = 0, > .has_mslice_steering = 0, > .has_snoop = 1,
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index df7c261410f79..d4b51ececbb12 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -829,6 +829,7 @@ static const struct intel_device_info mtl_info = { .has_flat_ccs = 0, .has_gmd_id = 1, .has_guc_deprivilege = 1, + .has_guc_tlb_invalidation = 1, .has_llc = 0, .has_mslice_steering = 0, .has_snoop = 1,