diff mbox series

[3/4] drm/i915: Move the DPLL extra power domain handling up one level

Message ID 20231012123522.26045-4-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: DPLL code cleanups | expand

Commit Message

Ville Syrjälä Oct. 12, 2023, 12:35 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The extra DPLL power domain is currently handled in three places:
- combo_pll_enable()
- combo_pll_disable()
- readout_dpll_hw_state()

First two of those are low level PLL funcs, but the third is a higher
level thing. So the current situation is rather inconsistent. Unify
this by moving the PLL enable/disable up one level. This also means
the extra power domain could be trivially be used by other platforms
as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

Comments

Jani Nikula Oct. 12, 2023, 2:56 p.m. UTC | #1 
On Thu, 12 Oct 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The extra DPLL power domain is currently handled in three places:
> - combo_pll_enable()
> - combo_pll_disable()
> - readout_dpll_hw_state()
>
> First two of those are low level PLL funcs, but the third is a higher
> level thing. So the current situation is rather inconsistent. Unify
> this by moving the PLL enable/disable up one level. This also means
> the extra power domain could be trivially be used by other platforms
> as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++++++++++------
>  1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 4e524cb8ed83..556b10eefe66 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -258,6 +258,10 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
>  	drm_WARN_ON(&i915->drm, pll->on);
>  
>  	drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name);
> +
> +	if (pll->info->power_domain)
> +		pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
> +
>  	pll->info->funcs->enable(i915, pll);
>  	pll->on = true;
>  
> @@ -307,6 +311,9 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
>  	pll->info->funcs->disable(i915, pll);
>  	pll->on = false;
>  
> +	if (pll->info->power_domain)
> +		intel_display_power_put(i915, pll->info->power_domain, pll->wakeref);
> +
>  out:
>  	mutex_unlock(&i915->display.dpll.lock);
>  }
> @@ -3838,9 +3845,6 @@ static void combo_pll_enable(struct drm_i915_private *i915,
>  {
>  	i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
>  
> -	if (pll->info->power_domain)
> -		pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
> -
>  	icl_pll_power_enable(i915, pll, enable_reg);
>  
>  	icl_dpll_write(i915, pll);
> @@ -3936,9 +3940,6 @@ static void combo_pll_disable(struct drm_i915_private *i915,
>  	i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
>  
>  	icl_pll_disable(i915, pll, enable_reg);
> -
> -	if (pll->info->power_domain)
> -		intel_display_power_put(i915, pll->info->power_domain, pll->wakeref);
>  }
>  
>  static void tbt_pll_disable(struct drm_i915_private *i915,
> @@ -4409,6 +4410,9 @@ static void sanitize_dpll_state(struct drm_i915_private *i915,
>  
>  	pll->info->funcs->disable(i915, pll);
>  	pll->on = false;
> +
> +	if (pll->info->power_domain)
> +		intel_display_power_put(i915, pll->info->power_domain, pll->wakeref);
>  }
>  
>  void intel_dpll_sanitize_state(struct drm_i915_private *i915)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4e524cb8ed83..556b10eefe66 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -258,6 +258,10 @@  void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
 	drm_WARN_ON(&i915->drm, pll->on);
 
 	drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name);
+
+	if (pll->info->power_domain)
+		pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
+
 	pll->info->funcs->enable(i915, pll);
 	pll->on = true;
 
@@ -307,6 +311,9 @@  void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 	pll->info->funcs->disable(i915, pll);
 	pll->on = false;
 
+	if (pll->info->power_domain)
+		intel_display_power_put(i915, pll->info->power_domain, pll->wakeref);
+
 out:
 	mutex_unlock(&i915->display.dpll.lock);
 }
@@ -3838,9 +3845,6 @@  static void combo_pll_enable(struct drm_i915_private *i915,
 {
 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
 
-	if (pll->info->power_domain)
-		pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
-
 	icl_pll_power_enable(i915, pll, enable_reg);
 
 	icl_dpll_write(i915, pll);
@@ -3936,9 +3940,6 @@  static void combo_pll_disable(struct drm_i915_private *i915,
 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
 
 	icl_pll_disable(i915, pll, enable_reg);
-
-	if (pll->info->power_domain)
-		intel_display_power_put(i915, pll->info->power_domain, pll->wakeref);
 }
 
 static void tbt_pll_disable(struct drm_i915_private *i915,
@@ -4409,6 +4410,9 @@  static void sanitize_dpll_state(struct drm_i915_private *i915,
 
 	pll->info->funcs->disable(i915, pll);
 	pll->on = false;
+
+	if (pll->info->power_domain)
+		intel_display_power_put(i915, pll->info->power_domain, pll->wakeref);
 }
 
 void intel_dpll_sanitize_state(struct drm_i915_private *i915)