| Message ID | 20231010062917.3624223-2-xianwei.zhao@amlogic.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add C3 SoC PLLs and Peripheral clock | expand |
Hi Rob,
Thanks for your advise.
On 2023/10/10 21:21, Rob Herring wrote:
> [ EXTERNAL EMAIL ]
>
> On Tue, Oct 10, 2023 at 02:29:14PM +0800, Xianwei Zhao wrote:
>> Add the C3 PLL clock controller dt-bindings for Amlogic C3 SoC family
>>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> V1 -> V2: Fix errors when check dtbinding use "make dt_binding_check"
>
> Your patches aren't bisectable. It's fine if you want to combine patch 1
> and 2 into 1 patch. Or just use the raw numbers here instead of the
> header.
>
I will combine patch 1 and 2 into 1 patch in V3.
>> ---
>> .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +++++++++++++++++++
>> .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 +++++++++++++
>> 2 files changed, 101 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>> create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>> new file mode 100644
>> index 000000000000..a646992917b7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>> @@ -0,0 +1,59 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Amlogic C3 serials PLL Clock Controller
>
> s/serials/Serials/
>
Will fix
>> +
>> +maintainers:
>> + - Chuan Liu <chuan.liu@amlogic.com>
>> +
>> +properties:
>> + compatible:
>> + const: amlogic,c3-pll-clkc
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + minItems: 1
>> + items:
>> + - description: input pll_in
>> + - description: input mclk_pll_in
>> +
>> + clock-names:
>> + minItems: 1
>> + items:
>> + - const: pll_in
>> + - const: mclk_pll_in
>> +
>> + "#clock-cells":
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - "#clock-cells"
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
>> + apb {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + clkc_pll: clock-controller@8000 {
>
> Drop unused labels.
>
Will delete clkc_pll.
>> + compatible = "amlogic,c3-pll-clkc";
>
> Your indentation is not consistent.
>
Will fix it in V3.
>> + reg = <0x0 0x8000 0x0 0x1a4>;
>> + clocks = <&clkc_periphs CLKID_PLL_IN>,
>> + <&clkc_periphs CLKID_MCLK_PLL_IN>;
>> + clock-names = "pll_in", "mclk_pll_in";
>> + #clock-cells = <1>;
>> + };
>> + };
>> diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
>> new file mode 100644
>> index 000000000000..aa731e8fae29
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
>> @@ -0,0 +1,42 @@
>> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
>> +/*
>> + * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
>> + * Author: Chuan Liu <chuan.liu@amlogic.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
>> +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
>> +
>> +#define CLKID_FIXED_PLL_DCO 0
>> +#define CLKID_FIXED_PLL 1
>> +#define CLKID_FCLK_DIV40_DIV 2
>> +#define CLKID_FCLK_DIV40 3
>> +#define CLKID_FCLK_DIV2_DIV 4
>> +#define CLKID_FCLK_DIV2 5
>> +#define CLKID_FCLK_DIV2P5_DIV 6
>> +#define CLKID_FCLK_DIV2P5 7
>> +#define CLKID_FCLK_DIV3_DIV 8
>> +#define CLKID_FCLK_DIV3 9
>> +#define CLKID_FCLK_DIV4_DIV 10
>> +#define CLKID_FCLK_DIV4 11
>> +#define CLKID_FCLK_DIV5_DIV 12
>> +#define CLKID_FCLK_DIV5 13
>> +#define CLKID_FCLK_DIV7_DIV 14
>> +#define CLKID_FCLK_DIV7 15
>> +#define CLKID_GP0_PLL_DCO 16
>> +#define CLKID_GP0_PLL 17
>> +#define CLKID_HIFI_PLL_DCO 18
>> +#define CLKID_HIFI_PLL 19
>> +#define CLKID_MCLK_PLL_DCO 20
>> +#define CLKID_MCLK_PLL 21
>> +#define CLKID_MCLK_PLL_CLK 22
>> +#define CLKID_MCLK0_SEL 23
>> +#define CLKID_MCLK0_SEL_OUT 24
>> +#define CLKID_MCLK0_DIV 25
>> +#define CLKID_MCLK0 26
>> +#define CLKID_MCLK1_SEL 27
>> +#define CLKID_MCLK1_SEL_OUT 28
>> +#define CLKID_MCLK1_DIV 29
>> +#define CLKID_MCLK1 30
>> +
>> +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */
>>
>> base-commit: 57b55c76aaf1ba50ecc6dcee5cd6843dc4d85239
>> --
>> 2.37.1
>>
On Wed 11 Oct 2023 at 10:50, Xianwei Zhao <xianwei.zhao@amlogic.com> wrote: > Hi Rob, > Thanks for your advise. > > On 2023/10/10 21:21, Rob Herring wrote: >> [ EXTERNAL EMAIL ] >> On Tue, Oct 10, 2023 at 02:29:14PM +0800, Xianwei Zhao wrote: >>> Add the C3 PLL clock controller dt-bindings for Amlogic C3 SoC family >>> >>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> >>> --- >>> V1 -> V2: Fix errors when check dtbinding use "make dt_binding_check" >> Your patches aren't bisectable. It's fine if you want to combine patch 1 >> and 2 into 1 patch. Or just use the raw numbers here instead of the >> header. >> > I will combine patch 1 and 2 into 1 patch in V3. I'd prefer if you used raw ids or even fake node for the example, like <&pll_in> and <&mpll_in> for readability, rather than combining the patches >>> --- >>> .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +++++++++++++++++++ >>> .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 +++++++++++++ >>> 2 files changed, 101 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml >>> create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h >>> >>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml >>> new file mode 100644 >>> index 000000000000..a646992917b7 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml >>> @@ -0,0 +1,59 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Amlogic C3 serials PLL Clock Controller >> s/serials/Serials/ >> > Will fix >>> + >>> +maintainers: >>> + - Chuan Liu <chuan.liu@amlogic.com> >>> + >>> +properties: >>> + compatible: >>> + const: amlogic,c3-pll-clkc >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + clocks: >>> + minItems: 1 >>> + items: >>> + - description: input pll_in >>> + - description: input mclk_pll_in >>> + >>> + clock-names: >>> + minItems: 1 >>> + items: >>> + - const: pll_in >>> + - const: mclk_pll_in >>> + >>> + "#clock-cells": >>> + const: 1 >>> + >>> +required: >>> + - compatible >>> + - reg >>> + - clocks >>> + - clock-names >>> + - "#clock-cells" >>> + >>> +additionalProperties: false >>> + >>> +examples: >>> + - | >>> + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h> >>> + apb { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + clkc_pll: clock-controller@8000 { >> Drop unused labels. >> > Will delete clkc_pll. >>> + compatible = "amlogic,c3-pll-clkc"; >> Your indentation is not consistent. >> > Will fix it in V3. >>> + reg = <0x0 0x8000 0x0 0x1a4>; >>> + clocks = <&clkc_periphs CLKID_PLL_IN>, >>> + <&clkc_periphs CLKID_MCLK_PLL_IN>; >>> + clock-names = "pll_in", "mclk_pll_in"; >>> + #clock-cells = <1>; >>> + }; >>> + }; >>> diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h >>> new file mode 100644 >>> index 000000000000..aa731e8fae29 >>> --- /dev/null >>> +++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h >>> @@ -0,0 +1,42 @@ >>> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ >>> +/* >>> + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. >>> + * Author: Chuan Liu <chuan.liu@amlogic.com> >>> + */ >>> + >>> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H >>> +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H >>> + >>> +#define CLKID_FIXED_PLL_DCO 0 >>> +#define CLKID_FIXED_PLL 1 >>> +#define CLKID_FCLK_DIV40_DIV 2 >>> +#define CLKID_FCLK_DIV40 3 >>> +#define CLKID_FCLK_DIV2_DIV 4 >>> +#define CLKID_FCLK_DIV2 5 >>> +#define CLKID_FCLK_DIV2P5_DIV 6 >>> +#define CLKID_FCLK_DIV2P5 7 >>> +#define CLKID_FCLK_DIV3_DIV 8 >>> +#define CLKID_FCLK_DIV3 9 >>> +#define CLKID_FCLK_DIV4_DIV 10 >>> +#define CLKID_FCLK_DIV4 11 >>> +#define CLKID_FCLK_DIV5_DIV 12 >>> +#define CLKID_FCLK_DIV5 13 >>> +#define CLKID_FCLK_DIV7_DIV 14 >>> +#define CLKID_FCLK_DIV7 15 >>> +#define CLKID_GP0_PLL_DCO 16 >>> +#define CLKID_GP0_PLL 17 >>> +#define CLKID_HIFI_PLL_DCO 18 >>> +#define CLKID_HIFI_PLL 19 >>> +#define CLKID_MCLK_PLL_DCO 20 >>> +#define CLKID_MCLK_PLL 21 >>> +#define CLKID_MCLK_PLL_CLK 22 >>> +#define CLKID_MCLK0_SEL 23 >>> +#define CLKID_MCLK0_SEL_OUT 24 >>> +#define CLKID_MCLK0_DIV 25 >>> +#define CLKID_MCLK0 26 >>> +#define CLKID_MCLK1_SEL 27 >>> +#define CLKID_MCLK1_SEL_OUT 28 >>> +#define CLKID_MCLK1_DIV 29 >>> +#define CLKID_MCLK1 30 >>> + >>> +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */ >>> >>> base-commit: 57b55c76aaf1ba50ecc6dcee5cd6843dc4d85239 >>> -- >>> 2.37.1 >>>
Hi Jerome,
Thanks for your reply.
On 2023/10/13 15:35, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed 11 Oct 2023 at 10:50, Xianwei Zhao <xianwei.zhao@amlogic.com> wrote:
>
>> Hi Rob,
>> Thanks for your advise.
>>
>> On 2023/10/10 21:21, Rob Herring wrote:
>>> [ EXTERNAL EMAIL ]
>>> On Tue, Oct 10, 2023 at 02:29:14PM +0800, Xianwei Zhao wrote:
>>>> Add the C3 PLL clock controller dt-bindings for Amlogic C3 SoC family
>>>>
>>>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>>>> ---
>>>> V1 -> V2: Fix errors when check dtbinding use "make dt_binding_check"
>>> Your patches aren't bisectable. It's fine if you want to combine patch 1
>>> and 2 into 1 patch. Or just use the raw numbers here instead of the
>>> header.
>>>
>> I will combine patch 1 and 2 into 1 patch in V3.
>
> I'd prefer if you used raw ids or even fake node for the example, like
> <&pll_in> and <&mpll_in> for readability, rather than combining the patches
>
Will do.
>>>> ---
>>>> .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +++++++++++++++++++
>>>> .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 +++++++++++++
>>>> 2 files changed, 101 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>>>> create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>>>> new file mode 100644
>>>> index 000000000000..a646992917b7
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>>>> @@ -0,0 +1,59 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Amlogic C3 serials PLL Clock Controller
>>> s/serials/Serials/
>>>
>> Will fix
>>>> +
>>>> +maintainers:
>>>> + - Chuan Liu <chuan.liu@amlogic.com>
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + const: amlogic,c3-pll-clkc
>>>> +
>>>> + reg:
>>>> + maxItems: 1
>>>> +
>>>> + clocks:
>>>> + minItems: 1
>>>> + items:
>>>> + - description: input pll_in
>>>> + - description: input mclk_pll_in
>>>> +
>>>> + clock-names:
>>>> + minItems: 1
>>>> + items:
>>>> + - const: pll_in
>>>> + - const: mclk_pll_in
>>>> +
>>>> + "#clock-cells":
>>>> + const: 1
>>>> +
>>>> +required:
>>>> + - compatible
>>>> + - reg
>>>> + - clocks
>>>> + - clock-names
>>>> + - "#clock-cells"
>>>> +
>>>> +additionalProperties: false
>>>> +
>>>> +examples:
>>>> + - |
>>>> + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
>>>> + apb {
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> +
>>>> + clkc_pll: clock-controller@8000 {
>>> Drop unused labels.
>>>
>> Will delete clkc_pll.
>>>> + compatible = "amlogic,c3-pll-clkc";
>>> Your indentation is not consistent.
>>>
>> Will fix it in V3.
>>>> + reg = <0x0 0x8000 0x0 0x1a4>;
>>>> + clocks = <&clkc_periphs CLKID_PLL_IN>,
>>>> + <&clkc_periphs CLKID_MCLK_PLL_IN>;
>>>> + clock-names = "pll_in", "mclk_pll_in";
>>>> + #clock-cells = <1>;
>>>> + };
>>>> + };
>>>> diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
>>>> new file mode 100644
>>>> index 000000000000..aa731e8fae29
>>>> --- /dev/null
>>>> +++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
>>>> @@ -0,0 +1,42 @@
>>>> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
>>>> +/*
>>>> + * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
>>>> + * Author: Chuan Liu <chuan.liu@amlogic.com>
>>>> + */
>>>> +
>>>> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
>>>> +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
>>>> +
>>>> +#define CLKID_FIXED_PLL_DCO 0
>>>> +#define CLKID_FIXED_PLL 1
>>>> +#define CLKID_FCLK_DIV40_DIV 2
>>>> +#define CLKID_FCLK_DIV40 3
>>>> +#define CLKID_FCLK_DIV2_DIV 4
>>>> +#define CLKID_FCLK_DIV2 5
>>>> +#define CLKID_FCLK_DIV2P5_DIV 6
>>>> +#define CLKID_FCLK_DIV2P5 7
>>>> +#define CLKID_FCLK_DIV3_DIV 8
>>>> +#define CLKID_FCLK_DIV3 9
>>>> +#define CLKID_FCLK_DIV4_DIV 10
>>>> +#define CLKID_FCLK_DIV4 11
>>>> +#define CLKID_FCLK_DIV5_DIV 12
>>>> +#define CLKID_FCLK_DIV5 13
>>>> +#define CLKID_FCLK_DIV7_DIV 14
>>>> +#define CLKID_FCLK_DIV7 15
>>>> +#define CLKID_GP0_PLL_DCO 16
>>>> +#define CLKID_GP0_PLL 17
>>>> +#define CLKID_HIFI_PLL_DCO 18
>>>> +#define CLKID_HIFI_PLL 19
>>>> +#define CLKID_MCLK_PLL_DCO 20
>>>> +#define CLKID_MCLK_PLL 21
>>>> +#define CLKID_MCLK_PLL_CLK 22
>>>> +#define CLKID_MCLK0_SEL 23
>>>> +#define CLKID_MCLK0_SEL_OUT 24
>>>> +#define CLKID_MCLK0_DIV 25
>>>> +#define CLKID_MCLK0 26
>>>> +#define CLKID_MCLK1_SEL 27
>>>> +#define CLKID_MCLK1_SEL_OUT 28
>>>> +#define CLKID_MCLK1_DIV 29
>>>> +#define CLKID_MCLK1 30
>>>> +
>>>> +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */
>>>>
>>>> base-commit: 57b55c76aaf1ba50ecc6dcee5cd6843dc4d85239
>>>> --
>>>> 2.37.1
>>>>
>
diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml new file mode 100644 index 000000000000..a646992917b7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 serials PLL Clock Controller + +maintainers: + - Chuan Liu <chuan.liu@amlogic.com> + +properties: + compatible: + const: amlogic,c3-pll-clkc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: input pll_in + - description: input mclk_pll_in + + clock-names: + minItems: 1 + items: + - const: pll_in + - const: mclk_pll_in + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h> + apb { + #address-cells = <2>; + #size-cells = <2>; + + clkc_pll: clock-controller@8000 { + compatible = "amlogic,c3-pll-clkc"; + reg = <0x0 0x8000 0x0 0x1a4>; + clocks = <&clkc_periphs CLKID_PLL_IN>, + <&clkc_periphs CLKID_MCLK_PLL_IN>; + clock-names = "pll_in", "mclk_pll_in"; + #clock-cells = <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h new file mode 100644 index 000000000000..aa731e8fae29 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu <chuan.liu@amlogic.com> + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H + +#define CLKID_FIXED_PLL_DCO 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV40_DIV 2 +#define CLKID_FCLK_DIV40 3 +#define CLKID_FCLK_DIV2_DIV 4 +#define CLKID_FCLK_DIV2 5 +#define CLKID_FCLK_DIV2P5_DIV 6 +#define CLKID_FCLK_DIV2P5 7 +#define CLKID_FCLK_DIV3_DIV 8 +#define CLKID_FCLK_DIV3 9 +#define CLKID_FCLK_DIV4_DIV 10 +#define CLKID_FCLK_DIV4 11 +#define CLKID_FCLK_DIV5_DIV 12 +#define CLKID_FCLK_DIV5 13 +#define CLKID_FCLK_DIV7_DIV 14 +#define CLKID_FCLK_DIV7 15 +#define CLKID_GP0_PLL_DCO 16 +#define CLKID_GP0_PLL 17 +#define CLKID_HIFI_PLL_DCO 18 +#define CLKID_HIFI_PLL 19 +#define CLKID_MCLK_PLL_DCO 20 +#define CLKID_MCLK_PLL 21 +#define CLKID_MCLK_PLL_CLK 22 +#define CLKID_MCLK0_SEL 23 +#define CLKID_MCLK0_SEL_OUT 24 +#define CLKID_MCLK0_DIV 25 +#define CLKID_MCLK0 26 +#define CLKID_MCLK1_SEL 27 +#define CLKID_MCLK1_SEL_OUT 28 +#define CLKID_MCLK1_DIV 29 +#define CLKID_MCLK1 30 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */
Add the C3 PLL clock controller dt-bindings for Amlogic C3 SoC family Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> --- V1 -> V2: Fix errors when check dtbinding use "make dt_binding_check" --- .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +++++++++++++++++++ .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 42 +++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h base-commit: 57b55c76aaf1ba50ecc6dcee5cd6843dc4d85239