Message ID | 20231017194422.4124691-5-luc.michel@amd.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Various updates for the Cadence GEM model | expand |
>-----Original Message----- >From: Luc Michel <luc.michel@amd.com> >Sent: Wednesday, October 18, 2023 1:14 AM >To: qemu-devel@nongnu.org >Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E . >Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>; >Peter Maydell <peter.maydell@linaro.org>; Jason Wang ><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>; >Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic ><Frederic.Konrad@amd.com>; Boddu, Sai Pavan ><sai.pavan.boddu@amd.com> >Subject: [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG >register fields > >Use de FIELD macro to describe the NWCFG register fields. > >Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Regards, Sai Pavan >--- > hw/net/cadence_gem.c | 60 ++++++++++++++++++++++++++++--------------- >- > 1 file changed, 39 insertions(+), 21 deletions(-) > >diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index >2864f0940e..09f570b6fb 100644 >--- a/hw/net/cadence_gem.c >+++ b/hw/net/cadence_gem.c >@@ -77,10 +77,39 @@ REG32(NWCTRL, 0x0) /* Network Control reg */ > FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1) > FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1) > FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) > > REG32(NWCFG, 0x4) /* Network Config reg */ >+ FIELD(NWCFG, SPEED, 0, 1) >+ FIELD(NWCFG, FULL_DUPLEX, 1, 1) >+ FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1) >+ FIELD(NWCFG, JUMBO_FRAMES, 3, 1) >+ FIELD(NWCFG, PROMISC, 4, 1) >+ FIELD(NWCFG, NO_BROADCAST, 5, 1) >+ FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1) >+ FIELD(NWCFG, UNICAST_HASH_EN, 7, 1) >+ FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1) >+ FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1) >+ FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1) >+ FIELD(NWCFG, PCS_SELECT, 11, 1) >+ FIELD(NWCFG, RETRY_TEST, 12, 1) >+ FIELD(NWCFG, PAUSE_ENABLE, 13, 1) >+ FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2) >+ FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1) >+ FIELD(NWCFG, FCS_REMOVE, 17, 1) >+ FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3) >+ FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2) >+ FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1) >+ FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1) >+ FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1) >+ FIELD(NWCFG, IGNORE_RX_FCS, 26, 1) >+ FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1) >+ FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1) >+ FIELD(NWCFG, NSP_ACCEPT, 29, 1) >+ FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1) >+ FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1) >+ > REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /* >User IO reg */ REG32(DMACFG, 0x10) /* DMA Control reg */ >REG32(TXSTATUS, 0x14) /* TX Status reg */ REG32(RXQBASE, 0x18) /* RX Q >Base address reg */ @@ -234,21 +263,10 @@ >REG32(TYPE2_COMPARE_0_WORD_1, 0x704) > FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) > FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) > FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) > > /*****************************************/ >-#define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ >-#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len >err */ >-#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset >mask */ >-#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ >-#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame >*/ >-#define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash >match */ >-#define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash >match */ >-#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets >*/ >-#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ >-#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable >*/ >- > #define GEM_DMACFG_ADDR_64B (1U << 30) > #define GEM_DMACFG_TX_BD_EXT (1U << 29) > #define GEM_DMACFG_RX_BD_EXT (1U << 28) > #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask >*/ > #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ >@@ -480,21 +498,22 @@ static inline void rx_desc_set_sar(uint32_t *desc, int >sar_idx) static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, >0xFF }; > > static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) { > uint32_t size; >- if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { >+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { > size = s->regs[R_JUMBO_MAX_LEN]; > if (size > s->jumbo_max_len) { > size = s->jumbo_max_len; > qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg >cannot be" > " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); > } > } else if (tx) { > size = 1518; > } else { >- size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; >+ size = FIELD_EX32(s->regs[R_NWCFG], >+ NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518; > } > return size; > } > > static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) @@ -730,26 >+749,26 @@ static int gem_mac_address_filter(CadenceGEMState *s, const >uint8_t *packet) { > uint8_t *gem_spaddr; > int i, is_mc; > > /* Promiscuous mode? */ >- if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) { >+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { > return GEM_RX_PROMISCUOUS_ACCEPT; > } > > if (!memcmp(packet, broadcast_addr, 6)) { > /* Reject broadcast packets? */ >- if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) { >+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) { > return GEM_RX_REJECT; > } > return GEM_RX_BROADCAST_ACCEPT; > } > > /* Accept packets -w- hash match? */ > is_mc = is_multicast_ether_addr(packet); >- if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) || >- (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) { >+ if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, >MULTICAST_HASH_EN))) || >+ (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, >+ UNICAST_HASH_EN))) { > uint64_t buckets; > unsigned hash_index; > > hash_index = calc_mac_hash(packet); > buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; @@ >-981,11 +1000,11 @@ static ssize_t gem_receive(NetClientState *nc, const >uint8_t *buf, size_t size) > if (maf == GEM_RX_REJECT) { > return size; /* no, drop silently b/c it's not an error */ > } > > /* Discard packets with receive length error enabled ? */ >- if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) { >+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) { > unsigned type_len; > > /* Fish the ethertype / length field out of the RX packet */ > type_len = buf[12] << 8 | buf[13]; > /* It is a length field, not an ethertype */ @@ -998,12 +1017,11 @@ static >ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) > } > > /* > * Determine configured receive buffer offset (probably 0) > */ >- rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> >- GEM_NWCFG_BUFF_OFST_S; >+ rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, >+ RECV_BUF_OFFSET); > > /* The configure size of each receive buffer. Determines how many > * buffers needed to hold this packet. > */ > rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> @@ - >1024,11 +1042,11 @@ static ssize_t gem_receive(NetClientState *nc, const >uint8_t *buf, size_t size) > if (size < 60) { > size = 60; > } > > /* Strip of FCS field ? (usually yes) */ >- if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) { >+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { > rxbuf_ptr = (void *)buf; > } else { > unsigned crc_val; > > if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { >-- >2.39.2
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 2864f0940e..09f570b6fb 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -77,10 +77,39 @@ REG32(NWCTRL, 0x0) /* Network Control reg */ FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1) FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1) FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) REG32(NWCFG, 0x4) /* Network Config reg */ + FIELD(NWCFG, SPEED, 0, 1) + FIELD(NWCFG, FULL_DUPLEX, 1, 1) + FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1) + FIELD(NWCFG, JUMBO_FRAMES, 3, 1) + FIELD(NWCFG, PROMISC, 4, 1) + FIELD(NWCFG, NO_BROADCAST, 5, 1) + FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1) + FIELD(NWCFG, UNICAST_HASH_EN, 7, 1) + FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1) + FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1) + FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1) + FIELD(NWCFG, PCS_SELECT, 11, 1) + FIELD(NWCFG, RETRY_TEST, 12, 1) + FIELD(NWCFG, PAUSE_ENABLE, 13, 1) + FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2) + FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1) + FIELD(NWCFG, FCS_REMOVE, 17, 1) + FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3) + FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2) + FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1) + FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1) + FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1) + FIELD(NWCFG, IGNORE_RX_FCS, 26, 1) + FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1) + FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1) + FIELD(NWCFG, NSP_ACCEPT, 29, 1) + FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1) + FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1) + REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /* User IO reg */ REG32(DMACFG, 0x10) /* DMA Control reg */ REG32(TXSTATUS, 0x14) /* TX Status reg */ REG32(RXQBASE, 0x18) /* RX Q Base address reg */ @@ -234,21 +263,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704) FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) /*****************************************/ -#define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ -#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ -#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ -#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ -#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */ -#define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ -#define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ -#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ -#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ -#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */ - #define GEM_DMACFG_ADDR_64B (1U << 30) #define GEM_DMACFG_TX_BD_EXT (1U << 29) #define GEM_DMACFG_RX_BD_EXT (1U << 28) #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ @@ -480,21 +498,22 @@ static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) { uint32_t size; - if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { + if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { size = s->regs[R_JUMBO_MAX_LEN]; if (size > s->jumbo_max_len) { size = s->jumbo_max_len; qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); } } else if (tx) { size = 1518; } else { - size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; + size = FIELD_EX32(s->regs[R_NWCFG], + NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518; } return size; } static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) @@ -730,26 +749,26 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) { uint8_t *gem_spaddr; int i, is_mc; /* Promiscuous mode? */ - if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) { + if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { return GEM_RX_PROMISCUOUS_ACCEPT; } if (!memcmp(packet, broadcast_addr, 6)) { /* Reject broadcast packets? */ - if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) { + if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) { return GEM_RX_REJECT; } return GEM_RX_BROADCAST_ACCEPT; } /* Accept packets -w- hash match? */ is_mc = is_multicast_ether_addr(packet); - if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) || - (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) { + if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) || + (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) { uint64_t buckets; unsigned hash_index; hash_index = calc_mac_hash(packet); buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; @@ -981,11 +1000,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) if (maf == GEM_RX_REJECT) { return size; /* no, drop silently b/c it's not an error */ } /* Discard packets with receive length error enabled ? */ - if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) { + if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) { unsigned type_len; /* Fish the ethertype / length field out of the RX packet */ type_len = buf[12] << 8 | buf[13]; /* It is a length field, not an ethertype */ @@ -998,12 +1017,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) } /* * Determine configured receive buffer offset (probably 0) */ - rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> - GEM_NWCFG_BUFF_OFST_S; + rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET); /* The configure size of each receive buffer. Determines how many * buffers needed to hold this packet. */ rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> @@ -1024,11 +1042,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) if (size < 60) { size = 60; } /* Strip of FCS field ? (usually yes) */ - if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) { + if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { rxbuf_ptr = (void *)buf; } else { unsigned crc_val; if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
Use de FIELD macro to describe the NWCFG register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> --- hw/net/cadence_gem.c | 60 ++++++++++++++++++++++++++++---------------- 1 file changed, 39 insertions(+), 21 deletions(-)