@@ -107,6 +107,36 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined
in version 1.0 of the Scalar Crypto ISA extensions.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
+ defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
@@ -39,6 +39,16 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZKSED (1 << 13)
#define RISCV_HWPROBE_EXT_ZKSH (1 << 14)
#define RISCV_HWPROBE_EXT_ZKT (1 << 15)
+#define RISCV_HWPROBE_EXT_ZVBB (1 << 16)
+#define RISCV_HWPROBE_EXT_ZVBC (1 << 17)
+#define RISCV_HWPROBE_EXT_ZVKB (1 << 18)
+#define RISCV_HWPROBE_EXT_ZVKG (1 << 19)
+#define RISCV_HWPROBE_EXT_ZVKNED (1 << 20)
+#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 21)
+#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 22)
+#define RISCV_HWPROBE_EXT_ZVKSED (1 << 23)
+#define RISCV_HWPROBE_EXT_ZVKSH (1 << 24)
+#define RISCV_HWPROBE_EXT_ZVKT (1 << 25)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
@@ -172,6 +172,19 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
CHECK_ISA_EXT(ZKSED);
CHECK_ISA_EXT(ZKSH);
CHECK_ISA_EXT(ZKT);
+
+ if (has_vector()) {
+ CHECK_ISA_EXT(ZVBB);
+ CHECK_ISA_EXT(ZVBC);
+ CHECK_ISA_EXT(ZVKB);
+ CHECK_ISA_EXT(ZVKG);
+ CHECK_ISA_EXT(ZVKNED);
+ CHECK_ISA_EXT(ZVKNHA);
+ CHECK_ISA_EXT(ZVKNHB);
+ CHECK_ISA_EXT(ZVKSED);
+ CHECK_ISA_EXT(ZVKSH);
+ CHECK_ISA_EXT(ZVKT);
+ }
#undef CHECK_ISA_EXT
}
Export Zv* vector crypto ISA extensions that were added in "RISC-V Cryptography Extensions Volume II" specification[1] through hwprobe. This adds support for the following instructions: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Zvkn and Zvks are ommited since they are a superset of other extensions. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> --- Documentation/riscv/hwprobe.rst | 30 +++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++++++ arch/riscv/kernel/sys_riscv.c | 13 ++++++++++++ 3 files changed, 53 insertions(+)