| Message ID | 20230926-topic-a643-v1-5-7af6937ac0a3@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Adreno 643 + fixes | expand |
On Tue, Sep 26, 2023 at 08:24:40PM +0200, Konrad Dybcio wrote: > > GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute). > On platforms that support it (in firmware), it is necessary to > describe that link, or Adreno register access will hang the board. > > Add that and fix up the SMR mask of SID 0, which seems to have been > copypasted from another SoC. > > Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index c38ddf267ef5..0d96d1454c49 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -2603,7 +2603,8 @@ gpu: gpu@3d00000 { > "cx_mem", > "cx_dbgc"; > interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; > - iommus = <&adreno_smmu 0 0x401>; > + iommus = <&adreno_smmu 0 0x400>, > + <&adreno_smmu 1 0x400>; Aren't both functionally same? 401 works fine on sc7280. You might be having issue due to Qcom TZ policies on your platform. I am okay with the change, but can you please reword the commit text? -Akhil. > operating-points-v2 = <&gpu_opp_table>; > qcom,gmu = <&gmu>; > interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; > > -- > 2.42.0 >
On 10/16/23 22:22, Akhil P Oommen wrote: > On Tue, Sep 26, 2023 at 08:24:40PM +0200, Konrad Dybcio wrote: >> >> GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute). >> On platforms that support it (in firmware), it is necessary to >> describe that link, or Adreno register access will hang the board. >> >> Add that and fix up the SMR mask of SID 0, which seems to have been >> copypasted from another SoC. >> >> Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index c38ddf267ef5..0d96d1454c49 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -2603,7 +2603,8 @@ gpu: gpu@3d00000 { >> "cx_mem", >> "cx_dbgc"; >> interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; >> - iommus = <&adreno_smmu 0 0x401>; >> + iommus = <&adreno_smmu 0 0x400>, >> + <&adreno_smmu 1 0x400>; > Aren't both functionally same? 401 works fine on sc7280. You might be > having issue due to Qcom TZ policies on your platform. I am okay with the change, but can > you please reword the commit text? Hm, looking at what the SMR registers represent, it looks like they should do the same thing and it may indeed be down to the TZ being picky.. I'll rephrase. Konrad
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index c38ddf267ef5..0d96d1454c49 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2603,7 +2603,8 @@ gpu: gpu@3d00000 { "cx_mem", "cx_dbgc"; interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&adreno_smmu 0 0x401>; + iommus = <&adreno_smmu 0 0x400>, + <&adreno_smmu 1 0x400>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute). On platforms that support it (in firmware), it is necessary to describe that link, or Adreno register access will hang the board. Add that and fix up the SMR mask of SID 0, which seems to have been copypasted from another SoC. Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)