| Message ID | 20231020120912.1888023-3-andrzej.hajda@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Apply Wa_16018031267 / Wa_16018063123 | expand |
-----Original Message----- From: Hajda, Andrzej <andrzej.hajda@intel.com> Sent: Friday, October 20, 2023 5:09 AM To: intel-gfx@lists.freedesktop.org Cc: Nirmoy Das <nirmoy.das@linux.intel.com>; Shyti, Andi <andi.shyti@intel.com>; Cavitt, Jonathan <jonathan.cavitt@intel.com>; Hajda, Andrzej <andrzej.hajda@intel.com>; Chris Wilson <chris.p.wilson@linux.intel.com> Subject: [PATCH v2 2/4] drm/i915: Reserve some kernel space per vm > > Reserve two pages in each vm for kernel space to use for things > such as workarounds. > > v2: use real memory, do not decrease vm.total Would XY_FAST_COLOR_BLIT be able to target this memory region? I'd have to ask Chris about this: He's better versed in this kind of stuff than I am. But I guess the answer must be "yes" if Chris suggested this change, so I won't block on this question. Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> -Jonathan Cavitt > > Suggested-by: Chris Wilson <chris.p.wilson@linux.intel.com> > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> > --- > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 38 ++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + > 2 files changed, 39 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > index 84aa29715e0aca..c25e1d4cceeb17 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > @@ -5,6 +5,7 @@ > > #include <linux/log2.h> > > +#include "gem/i915_gem_internal.h" > #include "gem/i915_gem_lmem.h" > > #include "gen8_ppgtt.h" > @@ -953,6 +954,39 @@ gen8_alloc_top_pd(struct i915_address_space *vm) > return ERR_PTR(err); > } > > +static int gen8_init_rsvd(struct i915_address_space *vm) > +{ > + const resource_size_t size = 2 * PAGE_SIZE; > + struct drm_i915_private *i915 = vm->i915; > + struct drm_i915_gem_object *obj; > + struct i915_vma *vma; > + int ret; > + > + obj = i915_gem_object_create_lmem(i915, size, > + I915_BO_ALLOC_VOLATILE | > + I915_BO_ALLOC_GPU_ONLY); > + if (IS_ERR(obj)) > + obj = i915_gem_object_create_internal(i915, size); > + if (IS_ERR(obj)) > + return PTR_ERR(obj); > + > + vma = i915_vma_instance(obj, vm, NULL); > + if (IS_ERR(vma)) { > + ret = PTR_ERR(vma); > + goto unref; > + } > + > + ret = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); > + if (ret) > + goto unref; > + > + vm->rsvd = i915_vma_make_unshrinkable(vma); > + > +unref: > + i915_gem_object_put(obj); > + return ret; > +} > + > /* > * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers > * with a net effect resembling a 2-level page table in normal x86 terms. Each > @@ -1034,6 +1068,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt, > if (intel_vgpu_active(gt->i915)) > gen8_ppgtt_notify_vgt(ppgtt, true); > > + err = gen8_init_rsvd(&ppgtt->vm); > + if (err) > + goto err_put; > + > return ppgtt; > > err_put: > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h > index 15c71da14d1d27..4a35ef24501b5f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h > @@ -250,6 +250,7 @@ struct i915_address_space { > struct work_struct release_work; > > struct drm_mm mm; > + struct i915_vma *rsvd; > struct intel_gt *gt; > struct drm_i915_private *i915; > struct device *dma; > -- > 2.34.1 > >
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 84aa29715e0aca..c25e1d4cceeb17 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -5,6 +5,7 @@ #include <linux/log2.h> +#include "gem/i915_gem_internal.h" #include "gem/i915_gem_lmem.h" #include "gen8_ppgtt.h" @@ -953,6 +954,39 @@ gen8_alloc_top_pd(struct i915_address_space *vm) return ERR_PTR(err); } +static int gen8_init_rsvd(struct i915_address_space *vm) +{ + const resource_size_t size = 2 * PAGE_SIZE; + struct drm_i915_private *i915 = vm->i915; + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + int ret; + + obj = i915_gem_object_create_lmem(i915, size, + I915_BO_ALLOC_VOLATILE | + I915_BO_ALLOC_GPU_ONLY); + if (IS_ERR(obj)) + obj = i915_gem_object_create_internal(i915, size); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + vma = i915_vma_instance(obj, vm, NULL); + if (IS_ERR(vma)) { + ret = PTR_ERR(vma); + goto unref; + } + + ret = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); + if (ret) + goto unref; + + vm->rsvd = i915_vma_make_unshrinkable(vma); + +unref: + i915_gem_object_put(obj); + return ret; +} + /* * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers * with a net effect resembling a 2-level page table in normal x86 terms. Each @@ -1034,6 +1068,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt, if (intel_vgpu_active(gt->i915)) gen8_ppgtt_notify_vgt(ppgtt, true); + err = gen8_init_rsvd(&ppgtt->vm); + if (err) + goto err_put; + return ppgtt; err_put: diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 15c71da14d1d27..4a35ef24501b5f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -250,6 +250,7 @@ struct i915_address_space { struct work_struct release_work; struct drm_mm mm; + struct i915_vma *rsvd; struct intel_gt *gt; struct drm_i915_private *i915; struct device *dma;
Reserve two pages in each vm for kernel space to use for things such as workarounds. v2: use real memory, do not decrease vm.total Suggested-by: Chris Wilson <chris.p.wilson@linux.intel.com> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 38 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + 2 files changed, 39 insertions(+)