| Message ID | 20231023153029.269211-7-c@jia.je (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add LoongArch v1.1 instructions | expand |
On 10/23/23 08:29, Jiajie Chen wrote: > --- a/target/loongarch/insn_trans/trans_atomic.c.inc > +++ b/target/loongarch/insn_trans/trans_atomic.c.inc > @@ -17,6 +17,14 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop) > return true; > } > > +static bool gen_llacq(DisasContext *ctx, arg_rr *a, MemOp mop) > +{ > + arg_rr_i tmp_a = { > + .rd = a->rd, .rj = a->rj, .imm = 0 > + }; > + return gen_ll(ctx, &tmp_a, mop); > +} > + > static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop) > { > TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); > @@ -45,6 +53,14 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop) > return true; > } > > +static bool gen_screl(DisasContext *ctx, arg_rr *a, MemOp mop) > +{ > + arg_rr_i tmp_a = { > + .rd = a->rd, .rj = a->rj, .imm = 0 > + }; > + return gen_sc(ctx, &tmp_a, mop); > +} This is incorrect. You need to add the required memory barriers. Should be like - static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop) + static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop, bool acq) { ... + if (acq) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } return true; } - static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop) + static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop, bool rel) { ... + if (rel) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } tcg_gen_brcond_tl(TCG_COND_EQ, t0, cpu_lladdr, l1); ... } TRANS(ll_w, ALL, gen_ll, MO_TESL, false) TRANS(sc_w, ALL, gen_sc, MO_TESL, false) TRANS(ll_d, 64, gen_ll, MO_TEUQ, false) TRANS(sc_d, 64, gen_sc, MO_TEUQ, false) TRANS(llacq_w, LLACQ_SCREL, gen_ll, MO_TESL, true) TRANS(screl_w, LLACQ_SCREL, gen_sc, MO_TESL, true) TRANS(llacq_d, LLACQ_SCREL_64, gen_ll, MO_TEUQ, true) TRANS(screl_d, LLACQ_SCREL_64, gen_sc, MO_TEUQ, true) You should decode into a common argument format, rather than doing it by hand. @rr_i0 .... ........ ..... ..... rj:5 rd:5 &rr_i imm=0 llacq_w 0011 10000101 01111 00000 ..... ..... @rr_i0 screl_w 0011 10000101 01111 00001 ..... ..... @rr_i0 llacq_d 0011 10000101 01111 00010 ..... ..... @rr_i0 screl_d 0011 10000101 01111 00011 ..... ..... @rr_i0 r~
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 8f938effa8..f0a63d5484 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -158,6 +158,7 @@ FIELD(CPUCFG2, LAM, 22, 1) FIELD(CPUCFG2, FRECIPE, 25, 1) FIELD(CPUCFG2, LAM_BH, 27, 1) FIELD(CPUCFG2, LAMCAS, 28, 1) +FIELD(CPUCFG2, LLACQ_SCREL, 29, 1) /* cpucfg[3] bits */ FIELD(CPUCFG3, CCDMA, 0, 1) diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 9eb49fb5e3..8e02f51ddc 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -579,6 +579,10 @@ INSN(fldx_s, frr) INSN(fldx_d, frr) INSN(fstx_s, frr) INSN(fstx_d, frr) +INSN(llacq_w, rr) +INSN(screl_w, rr) +INSN(llacq_d, rr) +INSN(screl_d, rr) INSN(amcas_b, rrr) INSN(amcas_h, rrr) INSN(amcas_w, rrr) diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc index bea567fdaf..0c81fbd745 100644 --- a/target/loongarch/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/insn_trans/trans_atomic.c.inc @@ -17,6 +17,14 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop) return true; } +static bool gen_llacq(DisasContext *ctx, arg_rr *a, MemOp mop) +{ + arg_rr_i tmp_a = { + .rd = a->rd, .rj = a->rj, .imm = 0 + }; + return gen_ll(ctx, &tmp_a, mop); +} + static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); @@ -45,6 +53,14 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop) return true; } +static bool gen_screl(DisasContext *ctx, arg_rr *a, MemOp mop) +{ + arg_rr_i tmp_a = { + .rd = a->rd, .rj = a->rj, .imm = 0 + }; + return gen_sc(ctx, &tmp_a, mop); +} + static bool gen_cas(DisasContext *ctx, arg_rrr *a, void (*func)(TCGv, TCGv, TCGv, TCGv, TCGArg, MemOp), MemOp mop) @@ -89,6 +105,10 @@ TRANS(ll_w, ALL, gen_ll, MO_TESL) TRANS(sc_w, ALL, gen_sc, MO_TESL) TRANS(ll_d, 64, gen_ll, MO_TEUQ) TRANS(sc_d, 64, gen_sc, MO_TEUQ) +TRANS(llacq_w, LLACQ_SCREL, gen_llacq, MO_TESL) +TRANS(screl_w, LLACQ_SCREL, gen_screl, MO_TESL) +TRANS(llacq_d, LLACQ_SCREL_64, gen_llacq, MO_TEUQ) +TRANS(screl_d, LLACQ_SCREL_64, gen_screl, MO_TEUQ) TRANS(amcas_b, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_TESB) TRANS(amcas_h, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_TESW) TRANS(amcas_w, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_TESL) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 92078f0f9f..e056d492d3 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -261,6 +261,10 @@ ll_w 0010 0000 .............. ..... ..... @rr_i14s2 sc_w 0010 0001 .............. ..... ..... @rr_i14s2 ll_d 0010 0010 .............. ..... ..... @rr_i14s2 sc_d 0010 0011 .............. ..... ..... @rr_i14s2 +llacq_w 0011 10000101 01111 00000 ..... ..... @rr +screl_w 0011 10000101 01111 00001 ..... ..... @rr +llacq_d 0011 10000101 01111 00010 ..... ..... @rr +screl_d 0011 10000101 01111 00011 ..... ..... @rr amcas_b 0011 10000101 10000 ..... ..... ..... @rrr amcas_h 0011 10000101 10001 ..... ..... ..... @rrr amcas_w 0011 10000101 10010 ..... ..... ..... @rrr diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index 651c5796ca..3d13d40ca6 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/translate.h @@ -34,6 +34,9 @@ #define avail_FRECIPE_LSX(C) (avail_FRECIPE(C) && avail_LSX(C)) #define avail_FRECIPE_LASX(C) (avail_FRECIPE(C) && avail_LASX(C)) +#define avail_LLACQ_SCREL(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LLACQ_SCREL)) +#define avail_LLACQ_SCREL_64(C) (avail_64(C) && avail_LLACQ_SCREL(C)) + /* * If an operation is being performed on less than TARGET_LONG_BITS, * it may require the inputs to be sign- or zero-extended; which will
Add the following instructions in LoongArch v1.1: - llacq.w - screl.w - llacq.d - screl.d They are guarded by CPUCFG2.LLACQ_SCREL. Signed-off-by: Jiajie Chen <c@jia.je> --- target/loongarch/cpu.h | 1 + target/loongarch/disas.c | 4 ++++ .../loongarch/insn_trans/trans_atomic.c.inc | 20 +++++++++++++++++++ target/loongarch/insns.decode | 4 ++++ target/loongarch/translate.h | 3 +++ 5 files changed, 32 insertions(+)