sbsa_gwdt: Calculate timeout with 64-bit math

Commit Message

Darren Hart Sept. 21, 2023, 9:02 a.m. UTC

Commit abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
introduced new timer math for watchdog revision 1 with the 48 bit offset
register.

The gwdt->clk and timeout are u32, but the argument being calculated is
u64. Without a cast, the compiler performs u32 operations, truncating
intermediate steps, resulting in incorrect values.

A watchdog revision 1 implementation with a gwdt->clk of 1GHz and a
timeout of 600s writes 3647256576 to the one shot watchdog instead of
300000000000, resulting in the watchdog firing in 3.6s instead of 600s.

Force u64 math by casting the first argument (gwdt->clk) as a u64. Make
the order of operations explicit with parenthesis.

Fixes: abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
Reported-by: Vanshidhar Konda <[e-mail]>
Signed-off-by: Darren Hart <[e-mail]>
Cc: Wim Van Sebroeck <[e-mail]>
Cc: Guenter Roeck <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
Cc: <[e-mail]> # 5.14.x
---
 drivers/watchdog/sbsa_gwdt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Guenter Roeck Sept. 26, 2023, 12:45 p.m. UTC | #1

On Thu, Sep 21, 2023 at 02:02:36AM -0700, Darren Hart wrote:
> Commit abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> introduced new timer math for watchdog revision 1 with the 48 bit offset
> register.
> 
> The gwdt->clk and timeout are u32, but the argument being calculated is
> u64. Without a cast, the compiler performs u32 operations, truncating
> intermediate steps, resulting in incorrect values.
> 
> A watchdog revision 1 implementation with a gwdt->clk of 1GHz and a
> timeout of 600s writes 3647256576 to the one shot watchdog instead of
> 300000000000, resulting in the watchdog firing in 3.6s instead of 600s.
> 
> Force u64 math by casting the first argument (gwdt->clk) as a u64. Make
> the order of operations explicit with parenthesis.
> 
> Fixes: abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> Reported-by: Vanshidhar Konda <[e-mail]>
> Signed-off-by: Darren Hart <[e-mail]>
> Cc: Wim Van Sebroeck <[e-mail]>
> Cc: Guenter Roeck <[e-mail]>
> Cc: [e-mail]
> Cc: [e-mail]
> Cc: [e-mail]
> Cc: <[e-mail]> # 5.14.x

Reviewed-by: Guenter Roeck <[e-mail]>

> ---
>  drivers/watchdog/sbsa_gwdt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
> index fd3cfdda4949..76527324b63c 100644
> --- a/drivers/watchdog/sbsa_gwdt.c
> +++ b/drivers/watchdog/sbsa_gwdt.c
> @@ -153,14 +153,14 @@ static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
>  	timeout = clamp_t(unsigned int, timeout, 1, wdd->max_hw_heartbeat_ms / 1000);
>  
>  	if (action)
> -		sbsa_gwdt_reg_write(gwdt->clk * timeout, gwdt);
> +		sbsa_gwdt_reg_write((u64)gwdt->clk * timeout, gwdt);
>  	else
>  		/*
>  		 * In the single stage mode, The first signal (WS0) is ignored,
>  		 * the timeout is (WOR * 2), so the WOR should be configured
>  		 * to half value of timeout.
>  		 */
> -		sbsa_gwdt_reg_write(gwdt->clk / 2 * timeout, gwdt);
> +		sbsa_gwdt_reg_write(((u64)gwdt->clk / 2) * timeout, gwdt);
>  
>  	return 0;
>  }
> -- 
> 2.41.0
>

Darren Hart Oct. 14, 2023, 9:12 a.m. UTC | #2

On Tue, Sep 26, 2023 at 05:45:13AM -0700, Guenter Roeck wrote:
> On Thu, Sep 21, 2023 at 02:02:36AM -0700, Darren Hart wrote:
> > Commit abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> > introduced new timer math for watchdog revision 1 with the 48 bit offset
> > register.
> > 
> > The gwdt->clk and timeout are u32, but the argument being calculated is
> > u64. Without a cast, the compiler performs u32 operations, truncating
> > intermediate steps, resulting in incorrect values.
> > 
> > A watchdog revision 1 implementation with a gwdt->clk of 1GHz and a
> > timeout of 600s writes 3647256576 to the one shot watchdog instead of
> > 300000000000, resulting in the watchdog firing in 3.6s instead of 600s.
> > 
> > Force u64 math by casting the first argument (gwdt->clk) as a u64. Make
> > the order of operations explicit with parenthesis.
> > 
> > Fixes: abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> > Reported-by: Vanshidhar Konda <[e-mail]>
> > Signed-off-by: Darren Hart <[e-mail]>
> > Cc: Wim Van Sebroeck <[e-mail]>
> > Cc: Guenter Roeck <[e-mail]>
> > Cc: [e-mail]
> > Cc: [e-mail]
> > Cc: [e-mail]
> > Cc: <[e-mail]> # 5.14.x
> 
> Reviewed-by: Guenter Roeck <[e-mail]>

Guenter or Wim, I haven't seen this land in the RCs or in next yet. Have
you already picked it up? Anything more needed from me?

Thanks,

Guenter Roeck Oct. 22, 2023, 4:58 p.m. UTC | #3

On 10/14/23 02:12, Darren Hart wrote:
> On Tue, Sep 26, 2023 at 05:45:13AM -0700, Guenter Roeck wrote:
>> On Thu, Sep 21, 2023 at 02:02:36AM -0700, Darren Hart wrote:
>>> Commit abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
>>> introduced new timer math for watchdog revision 1 with the 48 bit offset
>>> register.
>>>
>>> The gwdt->clk and timeout are u32, but the argument being calculated is
>>> u64. Without a cast, the compiler performs u32 operations, truncating
>>> intermediate steps, resulting in incorrect values.
>>>
>>> A watchdog revision 1 implementation with a gwdt->clk of 1GHz and a
>>> timeout of 600s writes 3647256576 to the one shot watchdog instead of
>>> 300000000000, resulting in the watchdog firing in 3.6s instead of 600s.
>>>
>>> Force u64 math by casting the first argument (gwdt->clk) as a u64. Make
>>> the order of operations explicit with parenthesis.
>>>
>>> Fixes: abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
>>> Reported-by: Vanshidhar Konda <[e-mail]>
>>> Signed-off-by: Darren Hart <[e-mail]>
>>> Cc: Wim Van Sebroeck <[e-mail]>
>>> Cc: Guenter Roeck <[e-mail]>
>>> Cc: [e-mail]
>>> Cc: [e-mail]
>>> Cc: [e-mail]
>>> Cc: <[e-mail]> # 5.14.x
>>
>> Reviewed-by: Guenter Roeck <[e-mail]>
> 
> Guenter or Wim, I haven't seen this land in the RCs or in next yet. Have
> you already picked it up? Anything more needed from me?
> 
> Thanks,
> 

Sorry, I am suffering from what I can only describe as a severe case of
maintainer/reviewer PTSD, and I have yet to find a way of dealing with that.

Guenter

Darren Hart Oct. 26, 2023, 5:17 p.m. UTC | #4

On Sun, Oct 22, 2023 at 09:58:26AM -0700, Guenter Roeck wrote:
> On 10/14/23 02:12, Darren Hart wrote:
> > On Tue, Sep 26, 2023 at 05:45:13AM -0700, Guenter Roeck wrote:
> > > On Thu, Sep 21, 2023 at 02:02:36AM -0700, Darren Hart wrote:
> > > > Commit abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> > > > introduced new timer math for watchdog revision 1 with the 48 bit offset
> > > > register.
> > > > 
> > > > The gwdt->clk and timeout are u32, but the argument being calculated is
> > > > u64. Without a cast, the compiler performs u32 operations, truncating
> > > > intermediate steps, resulting in incorrect values.
> > > > 
> > > > A watchdog revision 1 implementation with a gwdt->clk of 1GHz and a
> > > > timeout of 600s writes 3647256576 to the one shot watchdog instead of
> > > > 300000000000, resulting in the watchdog firing in 3.6s instead of 600s.
> > > > 
> > > > Force u64 math by casting the first argument (gwdt->clk) as a u64. Make
> > > > the order of operations explicit with parenthesis.
> > > > 
> > > > Fixes: abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> > > > Reported-by: Vanshidhar Konda <[e-mail]>
> > > > Signed-off-by: Darren Hart <[e-mail]>
> > > > Cc: Wim Van Sebroeck <[e-mail]>
> > > > Cc: Guenter Roeck <[e-mail]>
> > > > Cc: [e-mail]
> > > > Cc: [e-mail]
> > > > Cc: [e-mail]
> > > > Cc: <[e-mail]> # 5.14.x
> > > 
> > > Reviewed-by: Guenter Roeck <[e-mail]>
> > 
> > Guenter or Wim, I haven't seen this land in the RCs or in next yet. Have
> > you already picked it up? Anything more needed from me?
> > 
> > Thanks,
> > 
> 
> Sorry, I am suffering from what I can only describe as a severe case of
> maintainer/reviewer PTSD, and I have yet to find a way of dealing with that.
> 

I'm sorry to hear it Guenter, it can be a thankless slog of a treadmill
sometimes. I found having a co-maintainer a huge help to even out the human
factors while maintaining the x86 platform drivers (in the before times).

In the short term, should I ask if one of the Arm maintainers would be willing
to pick this patch up?

Thanks,

Wim Van Sebroeck Oct. 29, 2023, 3:53 p.m. UTC | #5

Hi Darren,

> On Sun, Oct 22, 2023 at 09:58:26AM -0700, Guenter Roeck wrote:
> > On 10/14/23 02:12, Darren Hart wrote:
> > > On Tue, Sep 26, 2023 at 05:45:13AM -0700, Guenter Roeck wrote:
> > > > On Thu, Sep 21, 2023 at 02:02:36AM -0700, Darren Hart wrote:
> > > > > Commit abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> > > > > introduced new timer math for watchdog revision 1 with the 48 bit offset
> > > > > register.
> > > > > 
> > > > > The gwdt->clk and timeout are u32, but the argument being calculated is
> > > > > u64. Without a cast, the compiler performs u32 operations, truncating
> > > > > intermediate steps, resulting in incorrect values.
> > > > > 
> > > > > A watchdog revision 1 implementation with a gwdt->clk of 1GHz and a
> > > > > timeout of 600s writes 3647256576 to the one shot watchdog instead of
> > > > > 300000000000, resulting in the watchdog firing in 3.6s instead of 600s.
> > > > > 
> > > > > Force u64 math by casting the first argument (gwdt->clk) as a u64. Make
> > > > > the order of operations explicit with parenthesis.
> > > > > 
> > > > > Fixes: abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> > > > > Reported-by: Vanshidhar Konda <[e-mail]>
> > > > > Signed-off-by: Darren Hart <[e-mail]>
> > > > > Cc: Wim Van Sebroeck <[e-mail]>
> > > > > Cc: Guenter Roeck <[e-mail]>
> > > > > Cc: [e-mail]
> > > > > Cc: [e-mail]
> > > > > Cc: [e-mail]
> > > > > Cc: <[e-mail]> # 5.14.x
> > > > 
> > > > Reviewed-by: Guenter Roeck <[e-mail]>
> > > 
> > > Guenter or Wim, I haven't seen this land in the RCs or in next yet. Have
> > > you already picked it up? Anything more needed from me?
> > > 
> > > Thanks,
> > > 
> > 
> > Sorry, I am suffering from what I can only describe as a severe case of
> > maintainer/reviewer PTSD, and I have yet to find a way of dealing with that.
> > 
> 
> I'm sorry to hear it Guenter, it can be a thankless slog of a treadmill
> sometimes. I found having a co-maintainer a huge help to even out the human
> factors while maintaining the x86 platform drivers (in the before times).
>
> In the short term, should I ask if one of the Arm maintainers would be willing
> to pick this patch up?

I'm picking this one up right now. So no need to ask it to the Arm maintainers.

Kind regards,
Wim.

Wim Van Sebroeck Oct. 29, 2023, 4:10 p.m. UTC | #6

Hi Guenter,

> On 10/14/23 02:12, Darren Hart wrote:
> >On Tue, Sep 26, 2023 at 05:45:13AM -0700, Guenter Roeck wrote:
> >>On Thu, Sep 21, 2023 at 02:02:36AM -0700, Darren Hart wrote:
> >>>Commit abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> >>>introduced new timer math for watchdog revision 1 with the 48 bit offset
> >>>register.
> >>>
> >>>The gwdt->clk and timeout are u32, but the argument being calculated is
> >>>u64. Without a cast, the compiler performs u32 operations, truncating
> >>>intermediate steps, resulting in incorrect values.
> >>>
> >>>A watchdog revision 1 implementation with a gwdt->clk of 1GHz and a
> >>>timeout of 600s writes 3647256576 to the one shot watchdog instead of
> >>>300000000000, resulting in the watchdog firing in 3.6s instead of 600s.
> >>>
> >>>Force u64 math by casting the first argument (gwdt->clk) as a u64. Make
> >>>the order of operations explicit with parenthesis.
> >>>
> >>>Fixes: abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> >>>Reported-by: Vanshidhar Konda <[e-mail]>
> >>>Signed-off-by: Darren Hart <[e-mail]>
> >>>Cc: Wim Van Sebroeck <[e-mail]>
> >>>Cc: Guenter Roeck <[e-mail]>
> >>>Cc: [e-mail]
> >>>Cc: [e-mail]
> >>>Cc: [e-mail]
> >>>Cc: <[e-mail]> # 5.14.x
> >>
> >>Reviewed-by: Guenter Roeck <[e-mail]>
> >
> >Guenter or Wim, I haven't seen this land in the RCs or in next yet. Have
> >you already picked it up? Anything more needed from me?
> >
> >Thanks,
> >
> 
> Sorry, I am suffering from what I can only describe as a severe case of
> maintainer/reviewer PTSD, and I have yet to find a way of dealing with that.

I can imagine what it is like. And I do know that if you wouldn't have been there, 
that I would have allready stopped being a maintainer. So I hope you can find the 
right cooping mechanisms. I also had to work non-stop the last 4 to 5 weeks and it was hell.
So I wish you all the best.

PS: picking up all patches that have your review-by tag on it as we speack.

Kind regards,
Wim.

Guenter Roeck Oct. 29, 2023, 5 p.m. UTC | #7

On 10/29/23 09:10, Wim Van Sebroeck wrote:
> Hi Guenter,
> 
>> On 10/14/23 02:12, Darren Hart wrote:
>>> On Tue, Sep 26, 2023 at 05:45:13AM -0700, Guenter Roeck wrote:
>>>> On Thu, Sep 21, 2023 at 02:02:36AM -0700, Darren Hart wrote:
>>>>> Commit abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
>>>>> introduced new timer math for watchdog revision 1 with the 48 bit offset
>>>>> register.
>>>>>
>>>>> The gwdt->clk and timeout are u32, but the argument being calculated is
>>>>> u64. Without a cast, the compiler performs u32 operations, truncating
>>>>> intermediate steps, resulting in incorrect values.
>>>>>
>>>>> A watchdog revision 1 implementation with a gwdt->clk of 1GHz and a
>>>>> timeout of 600s writes 3647256576 to the one shot watchdog instead of
>>>>> 300000000000, resulting in the watchdog firing in 3.6s instead of 600s.
>>>>>
>>>>> Force u64 math by casting the first argument (gwdt->clk) as a u64. Make
>>>>> the order of operations explicit with parenthesis.
>>>>>
>>>>> Fixes: abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
>>>>> Reported-by: Vanshidhar Konda <[e-mail]>
>>>>> Signed-off-by: Darren Hart <[e-mail]>
>>>>> Cc: Wim Van Sebroeck <[e-mail]>
>>>>> Cc: Guenter Roeck <[e-mail]>
>>>>> Cc: [e-mail]
>>>>> Cc: [e-mail]
>>>>> Cc: [e-mail]
>>>>> Cc: <[e-mail]> # 5.14.x
>>>>
>>>> Reviewed-by: Guenter Roeck <[e-mail]>
>>>
>>> Guenter or Wim, I haven't seen this land in the RCs or in next yet. Have
>>> you already picked it up? Anything more needed from me?
>>>
>>> Thanks,
>>>
>>
>> Sorry, I am suffering from what I can only describe as a severe case of
>> maintainer/reviewer PTSD, and I have yet to find a way of dealing with that.
> 
> I can imagine what it is like. And I do know that if you wouldn't have been there,
> that I would have allready stopped being a maintainer. So I hope you can find the
> right cooping mechanisms. I also had to work non-stop the last 4 to 5 weeks and it was hell.
> So I wish you all the best.
> 
> PS: picking up all patches that have your review-by tag on it as we speack.
> 

Thanks,
Guenter

Darren Hart Oct. 30, 2023, 4:21 p.m. UTC | #8

On Sun, Oct 29, 2023 at 10:00:54AM -0700, Guenter Roeck wrote:
> On 10/29/23 09:10, Wim Van Sebroeck wrote:
> > Hi Guenter,
> > 
> > > On 10/14/23 02:12, Darren Hart wrote:
> > > > On Tue, Sep 26, 2023 at 05:45:13AM -0700, Guenter Roeck wrote:
> > > > > On Thu, Sep 21, 2023 at 02:02:36AM -0700, Darren Hart wrote:
> > > > > > Commit abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> > > > > > introduced new timer math for watchdog revision 1 with the 48 bit offset
> > > > > > register.
> > > > > > 
> > > > > > The gwdt->clk and timeout are u32, but the argument being calculated is
> > > > > > u64. Without a cast, the compiler performs u32 operations, truncating
> > > > > > intermediate steps, resulting in incorrect values.
> > > > > > 
> > > > > > A watchdog revision 1 implementation with a gwdt->clk of 1GHz and a
> > > > > > timeout of 600s writes 3647256576 to the one shot watchdog instead of
> > > > > > 300000000000, resulting in the watchdog firing in 3.6s instead of 600s.
> > > > > > 
> > > > > > Force u64 math by casting the first argument (gwdt->clk) as a u64. Make
> > > > > > the order of operations explicit with parenthesis.
> > > > > > 
> > > > > > Fixes: abd3ac7902fb ("watchdog: sbsa: Support architecture version 1")
> > > > > > Reported-by: Vanshidhar Konda <[e-mail]>
> > > > > > Signed-off-by: Darren Hart <[e-mail]>
> > > > > > Cc: Wim Van Sebroeck <[e-mail]>
> > > > > > Cc: Guenter Roeck <[e-mail]>
> > > > > > Cc: [e-mail]
> > > > > > Cc: [e-mail]
> > > > > > Cc: [e-mail]
> > > > > > Cc: <[e-mail]> # 5.14.x
> > > > > 
> > > > > Reviewed-by: Guenter Roeck <[e-mail]>
> > > > 
> > > > Guenter or Wim, I haven't seen this land in the RCs or in next yet. Have
> > > > you already picked it up? Anything more needed from me?
> > > > 
> > > > Thanks,
> > > > 
> > > 
> > > Sorry, I am suffering from what I can only describe as a severe case of
> > > maintainer/reviewer PTSD, and I have yet to find a way of dealing with that.
> > 
> > I can imagine what it is like. And I do know that if you wouldn't have been there,
> > that I would have allready stopped being a maintainer. So I hope you can find the
> > right cooping mechanisms. I also had to work non-stop the last 4 to 5 weeks and it was hell.
> > So I wish you all the best.
> > 
> > PS: picking up all patches that have your review-by tag on it as we speack.
> > 
> 
> Thanks,
> Guenter

Thanks for the support Wim and Guenter. Appreciate the work you do and the
pressures of maintainership.

Patch

diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
index fd3cfdda4949..76527324b63c 100644
--- a/drivers/watchdog/sbsa_gwdt.c
+++ b/drivers/watchdog/sbsa_gwdt.c
@@ -153,14 +153,14 @@  static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
 	timeout = clamp_t(unsigned int, timeout, 1, wdd->max_hw_heartbeat_ms / 1000);
 
 	if (action)
-		sbsa_gwdt_reg_write(gwdt->clk * timeout, gwdt);
+		sbsa_gwdt_reg_write((u64)gwdt->clk * timeout, gwdt);
 	else
 		/*
 		 * In the single stage mode, The first signal (WS0) is ignored,
 		 * the timeout is (WOR * 2), so the WOR should be configured
 		 * to half value of timeout.
 		 */
-		sbsa_gwdt_reg_write(gwdt->clk / 2 * timeout, gwdt);
+		sbsa_gwdt_reg_write(((u64)gwdt->clk / 2) * timeout, gwdt);
 
 	return 0;
 }