| Message ID | 1698202408-14608-5-git-send-email-quic_taozha@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/8] dt-bindings: arm: Add support for CMB element size | expand |
On 25/10/2023 03:53, Tao Zhang wrote: > TPDM CMB subunits support two forms of CMB data set element creation: > continuous and trace-on-change collection mode. Continuous change > creates CMB data set elements on every CMBCLK edge. Trace-on-change > creates CMB data set elements only when a new data set element differs > in value from the previous element in a CMB data set. Set CMB_CR.MODE > to 0 for continuous CMB collection mode. Set CMB_CR.MODE to 1 for > trace-on-change CMB collection mode > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > Signed-off-by: Jinlong Mao <quic_jinlmao@quicinc.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 10 +++ > drivers/hwtracing/coresight/coresight-tpdm.c | 71 ++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++++ > 3 files changed, 93 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > index f07218e..ace7231 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > @@ -170,3 +170,13 @@ Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_t > Description: > (RW) Set/Get the MSR(mux select register) for the DSB subunit > TPDM. > + > +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode > +Date: March 2023 > +KernelVersion 6.7 > +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com> > +Description: (Write) Set the data collection mode of CMB tpdm. I know it's expanded elsewhere, but it's probably worth expanding the CMB abbreviation here as well so people reading the docs don't have to go into the code. Otherwise: Reviewed-by: James Clark <james.clark@arm.com> > + > + Accepts only one of the 2 values - 0 or 1. > + 0 : Continuous CMB collection mode. > + 1 : Trace-on-change CMB collection mode. > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index c8bb388..efb376e 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -148,6 +148,18 @@ static umode_t tpdm_dsb_is_visible(struct kobject *kobj, > return 0; > } [...]
On 10/30/2023 7:29 PM, James Clark wrote: > > On 25/10/2023 03:53, Tao Zhang wrote: >> TPDM CMB subunits support two forms of CMB data set element creation: >> continuous and trace-on-change collection mode. Continuous change >> creates CMB data set elements on every CMBCLK edge. Trace-on-change >> creates CMB data set elements only when a new data set element differs >> in value from the previous element in a CMB data set. Set CMB_CR.MODE >> to 0 for continuous CMB collection mode. Set CMB_CR.MODE to 1 for >> trace-on-change CMB collection mode >> >> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >> Signed-off-by: Jinlong Mao <quic_jinlmao@quicinc.com> >> --- >> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 10 +++ >> drivers/hwtracing/coresight/coresight-tpdm.c | 71 ++++++++++++++++++++++ >> drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++++ >> 3 files changed, 93 insertions(+) >> >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> index f07218e..ace7231 100644 >> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> @@ -170,3 +170,13 @@ Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_t >> Description: >> (RW) Set/Get the MSR(mux select register) for the DSB subunit >> TPDM. >> + >> +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode >> +Date: March 2023 >> +KernelVersion 6.7 >> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com> >> +Description: (Write) Set the data collection mode of CMB tpdm. > I know it's expanded elsewhere, but it's probably worth expanding the > CMB abbreviation here as well so people reading the docs don't have to > go into the code. Sure, I will update in the next patch series. Best, Tao > > Otherwise: > > Reviewed-by: James Clark <james.clark@arm.com> > >> + >> + Accepts only one of the 2 values - 0 or 1. >> + 0 : Continuous CMB collection mode. >> + 1 : Trace-on-change CMB collection mode. >> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c >> index c8bb388..efb376e 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpdm.c >> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c >> @@ -148,6 +148,18 @@ static umode_t tpdm_dsb_is_visible(struct kobject *kobj, >> return 0; >> } > [...]
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index f07218e..ace7231 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -170,3 +170,13 @@ Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_t Description: (RW) Set/Get the MSR(mux select register) for the DSB subunit TPDM. + +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode +Date: March 2023 +KernelVersion 6.7 +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com> +Description: (Write) Set the data collection mode of CMB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Continuous CMB collection mode. + 1 : Trace-on-change CMB collection mode. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index c8bb388..efb376e 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -148,6 +148,18 @@ static umode_t tpdm_dsb_is_visible(struct kobject *kobj, return 0; } +static umode_t tpdm_cmb_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (drvdata && tpdm_has_cmb_dataset(drvdata)) + return attr->mode; + + return 0; +} + static umode_t tpdm_dsb_msr_is_visible(struct kobject *kobj, struct attribute *attr, int n) { @@ -172,6 +184,9 @@ static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) drvdata->dsb->trig_ts = true; drvdata->dsb->trig_type = false; } + + if (tpdm_has_cmb_dataset(drvdata)) + memset(drvdata->cmb, 0, sizeof(struct cmb_dataset)); } static void set_dsb_mode(struct tpdm_drvdata *drvdata, u32 *val) @@ -277,6 +292,16 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) u32 val; val = readl_relaxed(drvdata->base + TPDM_CMB_CR); + /* + * Set to 0 for continuous CMB collection mode, + * 1 for trace-on-change CMB collection mode. + */ + if (drvdata->cmb->trace_mode) + val |= TPDM_CMB_CR_MODE; + else + val &= ~TPDM_CMB_CR_MODE; + + /* Set the enable bit of CMB control register to 1 */ val |= TPDM_CMB_CR_ENA; /* Set the enable bit of CMB control register to 1 */ @@ -397,6 +422,12 @@ static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) if (!drvdata->dsb) return -ENOMEM; } + if (tpdm_has_cmb_dataset(drvdata) && (!drvdata->cmb)) { + drvdata->cmb = devm_kzalloc(drvdata->dev, + sizeof(*drvdata->cmb), GFP_KERNEL); + if (!drvdata->cmb) + return -ENOMEM; + } tpdm_reset_datasets(drvdata); return 0; @@ -735,6 +766,35 @@ static ssize_t dsb_trig_ts_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_trig_ts); +static ssize_t cmb_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%x\n", + drvdata->cmb->trace_mode); + +} + +static ssize_t cmb_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long trace_mode; + + if ((kstrtoul(buf, 0, &trace_mode)) || (trace_mode & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->cmb->trace_mode = trace_mode; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cmb_mode); + static struct attribute *tpdm_dsb_edge_attrs[] = { &dev_attr_ctrl_idx.attr, &dev_attr_ctrl_val.attr, @@ -851,6 +911,11 @@ static struct attribute *tpdm_dsb_attrs[] = { NULL, }; +static struct attribute *tpdm_cmb_attrs[] = { + &dev_attr_cmb_mode.attr, + NULL, +}; + static struct attribute_group tpdm_dsb_attr_grp = { .attrs = tpdm_dsb_attrs, .is_visible = tpdm_dsb_is_visible, @@ -880,6 +945,11 @@ static struct attribute_group tpdm_dsb_msr_grp = { .name = "dsb_msr", }; +static struct attribute_group tpdm_cmb_attr_grp = { + .attrs = tpdm_cmb_attrs, + .is_visible = tpdm_cmb_is_visible, +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, &tpdm_dsb_attr_grp, @@ -887,6 +957,7 @@ static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_dsb_trig_patt_grp, &tpdm_dsb_patt_grp, &tpdm_dsb_msr_grp, + &tpdm_cmb_attr_grp, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 0098c58..c6b36d2 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -14,6 +14,8 @@ /* Enable bit for CMB subunit */ #define TPDM_CMB_CR_ENA BIT(0) +/* Trace collection mode for CMB subunit */ +#define TPDM_CMB_CR_MODE BIT(1) /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) @@ -182,6 +184,14 @@ struct dsb_dataset { }; /** + * struct cmb_dataset + * @trace_mode: Dataset collection mode + */ +struct cmb_dataset { + u32 trace_mode; +}; + +/** * struct tpdm_drvdata - specifics associated to an TPDM component * @base: memory mapped base address for this component. * @dev: The device entity associated to this component. @@ -190,6 +200,7 @@ struct dsb_dataset { * @enable: enable status of the component. * @datasets: The datasets types present of the TPDM. * @dsb Specifics associated to TPDM DSB. + * @cmb Specifics associated to TPDM CMB. * @dsb_msr_num Number of MSR supported by DSB TPDM */ @@ -201,6 +212,7 @@ struct tpdm_drvdata { bool enable; unsigned long datasets; struct dsb_dataset *dsb; + struct cmb_dataset *cmb; u32 dsb_msr_num; };