Message ID | 20231107105556.517187-7-cleger@rivosinc.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | riscv: report more ISA extensions through hwprobe | expand |
Context | Check | Description |
---|---|---|
conchuod/vmtest-fixes-PR | fail | merge-conflict |
On Nov 7, 2023, at 18:55, Clément Léger <cleger@rivosinc.com> wrote: > +static const unsigned int riscv_zvknhb_exts[] = { > + RISCV_ISA_EXT_ZVKNHA > +}; > + > + __RISCV_ISA_EXT_SUPERSET(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_zvknhb_exts), > + __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), The Zvknha and Zvknhb are exclusive. It's not the superset relationship. Please check: https://github.com/riscv/riscv-crypto/issues/364#issuecomment-1726782096 -Jerry
On Thu, Nov 09, 2023 at 10:58:41AM +0800, Jerry Shih wrote: > On Nov 7, 2023, at 18:55, Clément Léger <cleger@rivosinc.com> wrote: > > +static const unsigned int riscv_zvknhb_exts[] = { > > + RISCV_ISA_EXT_ZVKNHA > > +}; > > + > > > + __RISCV_ISA_EXT_SUPERSET(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_zvknhb_exts), > > + __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), > > The Zvknha and Zvknhb are exclusive. It's not the superset relationship. > > Please check: > https://github.com/riscv/riscv-crypto/issues/364#issuecomment-1726782096 You got a response to this on the previous version, but didn't engage with it: https://lore.kernel.org/all/c64d9ddb-edbd-4c8f-b56f-1b90d82100b7@rivosinc.com/#t Cheers, Conor.
On Thu, Nov 09, 2023 at 07:44:46AM +0000, Conor Dooley wrote: > On Thu, Nov 09, 2023 at 10:58:41AM +0800, Jerry Shih wrote: > > On Nov 7, 2023, at 18:55, Clément Léger <cleger@rivosinc.com> wrote: > > > +static const unsigned int riscv_zvknhb_exts[] = { > > > + RISCV_ISA_EXT_ZVKNHA > > > +}; > > > + > > > > > + __RISCV_ISA_EXT_SUPERSET(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_zvknhb_exts), > > > + __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), > > > > The Zvknha and Zvknhb are exclusive. It's not the superset relationship. > > > > Please check: > > https://github.com/riscv/riscv-crypto/issues/364#issuecomment-1726782096 > > You got a response to this on the previous version, but didn't engage > with it: > https://lore.kernel.org/all/c64d9ddb-edbd-4c8f-b56f-1b90d82100b7@rivosinc.com/#t Ahh, I now see what that happened. Your mailer is broken and puts the message-id of what you are replying to in the In-Reply-To and Reply-To headers. The former is correct, the latter is bogus & means you don't even get delivered the response.
On Nov 9, 2023, at 15:54, Conor Dooley <conor.dooley@microchip.com> wrote: > On Thu, Nov 09, 2023 at 07:44:46AM +0000, Conor Dooley wrote: >> On Thu, Nov 09, 2023 at 10:58:41AM +0800, Jerry Shih wrote: >>> On Nov 7, 2023, at 18:55, Clément Léger <cleger@rivosinc.com> wrote: >>> The Zvknha and Zvknhb are exclusive. It's not the superset relationship. >>> >>> Please check: >>> https://github.com/riscv/riscv-crypto/issues/364#issuecomment-1726782096 >> >> You got a response to this on the previous version, but didn't engage >> with it: >> https://lore.kernel.org/all/c64d9ddb-edbd-4c8f-b56f-1b90d82100b7@rivosinc.com/#t Reply for the thread: https://lore.kernel.org/all/c64d9ddb-edbd-4c8f-b56f-1b90d82100b7@rivosinc.com/#t > Yes, but for instance, what happens if the user query the zvknha (if it > only needs SHA256) but zvknhb is present. If we don't declare zvknha, > then it will fail but the support would actually be present due to > zvknhb being there. If we needs SHA256 only, then we should check whether we have zvknha `or` zvknhb. https://github.com/openssl/openssl/blob/4d4657cb6ba364dfa60681948b0a30c40bee31ca/crypto/sha/sha_riscv.c#L24 > Ahh, I now see what that happened. Your mailer is broken and puts the > message-id of what you are replying to in the In-Reply-To and Reply-To > headers. The former is correct, the latter is bogus & means you don't even > get delivered the response. I use mac builtin `mail` client. And I think I put the `in-reply-to` address to the `reply to` field. Hope this one works well. Thank you for the thread forwarding. -Jerry
On 09/11/2023 10:45, Jerry Shih wrote: > On Nov 9, 2023, at 15:54, Conor Dooley <conor.dooley@microchip.com> wrote: >> On Thu, Nov 09, 2023 at 07:44:46AM +0000, Conor Dooley wrote: >>> On Thu, Nov 09, 2023 at 10:58:41AM +0800, Jerry Shih wrote: >>>> On Nov 7, 2023, at 18:55, Clément Léger <cleger@rivosinc.com> wrote: >>>> The Zvknha and Zvknhb are exclusive. It's not the superset relationship. >>>> >>>> Please check: >>>> https://github.com/riscv/riscv-crypto/issues/364#issuecomment-1726782096 >>> >>> You got a response to this on the previous version, but didn't engage >>> with it: >>> https://lore.kernel.org/all/c64d9ddb-edbd-4c8f-b56f-1b90d82100b7@rivosinc.com/#t > > Reply for the thread: > https://lore.kernel.org/all/c64d9ddb-edbd-4c8f-b56f-1b90d82100b7@rivosinc.com/#t Hi Jerry, Sorry for that, I actually thought my mailer was broken and fixed the mail the first time I answered but not the second time... > >> Yes, but for instance, what happens if the user query the zvknha (if it >> only needs SHA256) but zvknhb is present. If we don't declare zvknha, >> then it will fail but the support would actually be present due to >> zvknhb being there. > > If we needs SHA256 only, then we should check whether we have zvknha `or` zvknhb. > https://github.com/openssl/openssl/blob/4d4657cb6ba364dfa60681948b0a30c40bee31ca/crypto/sha/sha_riscv.c#L24 Ok, and if there is already some userspace code that behaves like that, let's go this way and do not treat that as a superset. Thanks, Clément > >> Ahh, I now see what that happened. Your mailer is broken and puts the >> message-id of what you are replying to in the In-Reply-To and Reply-To >> headers. The former is correct, the latter is bogus & means you don't even >> get delivered the response. > > I use mac builtin `mail` client. And I think I put the `in-reply-to` address to > the `reply to` field. Hope this one works well. Thank you for the thread forwarding. > > -Jerry
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 69cc659cf65e..556d1da02877 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -71,8 +71,18 @@ #define RISCV_ISA_EXT_ZKSED 53 #define RISCV_ISA_EXT_ZKSH 54 #define RISCV_ISA_EXT_ZKT 55 - -#define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_ZVBB 56 +#define RISCV_ISA_EXT_ZVBC 57 +#define RISCV_ISA_EXT_ZVKB 58 +#define RISCV_ISA_EXT_ZVKG 59 +#define RISCV_ISA_EXT_ZVKNED 60 +#define RISCV_ISA_EXT_ZVKNHA 61 +#define RISCV_ISA_EXT_ZVKNHB 62 +#define RISCV_ISA_EXT_ZVKSED 63 +#define RISCV_ISA_EXT_ZVKSH 64 +#define RISCV_ISA_EXT_ZVKT 65 + +#define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX #ifdef CONFIG_RISCV_M_MODE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 0d78791288da..56570b838910 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -121,6 +121,10 @@ static bool riscv_isa_extension_check(int id) #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) +/* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ +#define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) + static const unsigned int riscv_zk_bundled_exts[] = { RISCV_ISA_EXT_ZBKB, RISCV_ISA_EXT_ZBKC, @@ -147,6 +151,54 @@ static const unsigned int riscv_zks_bundled_exts[] = { RISCV_ISA_EXT_ZKSH }; +#define RISCV_ISA_EXT_ZVKN \ + RISCV_ISA_EXT_ZVKNED, \ + RISCV_ISA_EXT_ZVKNHB, \ + RISCV_ISA_EXT_ZVKB, \ + RISCV_ISA_EXT_ZVKT + +static const unsigned int riscv_zvkn_bundled_exts[] = { + RISCV_ISA_EXT_ZVKN +}; + +static const unsigned int riscv_zvknc_bundled_exts[] = { + RISCV_ISA_EXT_ZVKN, + RISCV_ISA_EXT_ZVBC +}; + +static const unsigned int riscv_zvkng_bundled_exts[] = { + RISCV_ISA_EXT_ZVKN, + RISCV_ISA_EXT_ZVKG +}; + +#define RISCV_ISA_EXT_ZVKS \ + RISCV_ISA_EXT_ZVKSED, \ + RISCV_ISA_EXT_ZVKSH, \ + RISCV_ISA_EXT_ZVKB, \ + RISCV_ISA_EXT_ZVKT + +static const unsigned int riscv_zvks_bundled_exts[] = { + RISCV_ISA_EXT_ZVKS +}; + +static const unsigned int riscv_zvksc_bundled_exts[] = { + RISCV_ISA_EXT_ZVKS, + RISCV_ISA_EXT_ZVBC +}; + +static const unsigned int riscv_zvksg_bundled_exts[] = { + RISCV_ISA_EXT_ZVKS, + RISCV_ISA_EXT_ZVKG +}; + +static const unsigned int riscv_zvbb_exts[] = { + RISCV_ISA_EXT_ZVKB +}; + +static const unsigned int riscv_zvknhb_exts[] = { + RISCV_ISA_EXT_ZVKNHA +}; + /* * The canonical order of ISA extension names in the ISA string is defined in * chapter 27 of the unprivileged specification. @@ -225,6 +277,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), + __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), + __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), + __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts), + __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED), + __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts), + __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA), + __RISCV_ISA_EXT_SUPERSET(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_zvknhb_exts), + __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts), + __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED), + __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), + __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), + __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
Add parsing of some Zv* vector crypto ISA extensions that are mentioned in "RISC-V Cryptography Extensions Volume II" [1]. These ISA extensions are the following: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> --- arch/riscv/include/asm/hwcap.h | 14 ++++++- arch/riscv/kernel/cpufeature.c | 68 ++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+), 2 deletions(-)