| Message ID | 8-v2-de8b10590bf5+400-smmuv3_newapi_p1_jgg@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update SMMUv3 to the modern iommu API (part 1/3) | expand |
On Tue, Nov 14, 2023 at 1:53 AM Jason Gunthorpe <jgg@nvidia.com> wrote: > > Half the code was living in arm_smmu_domain_finalise_s2(), just move it > here and take the values directly from the pgtbl_ops instead of storing > copies. > > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Michael Shavit <mshavit@google.com> > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 27 ++++++++++++--------- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 -- > 2 files changed, 15 insertions(+), 14 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 1c63fdebbda9d4..e80373885d8b19 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1499,6 +1499,11 @@ static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, > struct arm_smmu_domain *smmu_domain) > { > struct arm_smmu_s2_cfg *s2_cfg = &smmu_domain->s2_cfg; > + const struct io_pgtable_cfg *pgtbl_cfg = > + &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; > + typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr = > + &pgtbl_cfg->arm_lpae_s2_cfg.vtcr; > + u64 vtcr_val; > > memset(target, 0, sizeof(*target)); > > @@ -1510,9 +1515,16 @@ static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, > FIELD_PREP(STRTAB_STE_1_EATS, > master->ats_enabled ? STRTAB_STE_1_EATS_TRANS : 0)); > > + vtcr_val = FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, vtcr->tsz) | > + FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, vtcr->sl) | > + FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, vtcr->irgn) | > + FIELD_PREP(STRTAB_STE_2_VTCR_S2OR0, vtcr->orgn) | > + FIELD_PREP(STRTAB_STE_2_VTCR_S2SH0, vtcr->sh) | > + FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | > + FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); > target->data[2] = cpu_to_le64( > FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | > - FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | > + FIELD_PREP(STRTAB_STE_2_VTCR, vtcr_val) | > STRTAB_STE_2_S2AA64 | > #ifdef __BIG_ENDIAN > STRTAB_STE_2_S2ENDI | > @@ -1520,7 +1532,8 @@ static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, > STRTAB_STE_2_S2PTW | > STRTAB_STE_2_S2R); > > - target->data[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); > + target->data[3] = cpu_to_le64(pgtbl_cfg->arm_lpae_s2_cfg.vttbr & > + STRTAB_STE_3_S2TTB_MASK); > } > > static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > @@ -2277,7 +2290,6 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, > int vmid; > struct arm_smmu_device *smmu = smmu_domain->smmu; > struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; > - typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr; > > /* Reserve VMID 0 for stage-2 bypass STEs */ > vmid = ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, > @@ -2285,16 +2297,7 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, > if (vmid < 0) > return vmid; > > - vtcr = &pgtbl_cfg->arm_lpae_s2_cfg.vtcr; > cfg->vmid = (u16)vmid; > - cfg->vttbr = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; > - cfg->vtcr = FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, vtcr->tsz) | > - FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, vtcr->sl) | > - FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, vtcr->irgn) | > - FIELD_PREP(STRTAB_STE_2_VTCR_S2OR0, vtcr->orgn) | > - FIELD_PREP(STRTAB_STE_2_VTCR_S2SH0, vtcr->sh) | > - FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | > - FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); > return 0; > } > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 27ddf1acd12cea..1be0c1151c50c3 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -609,8 +609,6 @@ struct arm_smmu_ctx_desc_cfg { > > struct arm_smmu_s2_cfg { > u16 vmid; > - u64 vttbr; > - u64 vtcr; > }; > > struct arm_smmu_strtab_cfg { > -- > 2.42.0 >
On Mon, Nov 13, 2023 at 01:53:15PM -0400, Jason Gunthorpe wrote: > Half the code was living in arm_smmu_domain_finalise_s2(), just move it > here and take the values directly from the pgtbl_ops instead of storing > copies. > > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 1c63fdebbda9d4..e80373885d8b19 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1499,6 +1499,11 @@ static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_domain *smmu_domain) { struct arm_smmu_s2_cfg *s2_cfg = &smmu_domain->s2_cfg; + const struct io_pgtable_cfg *pgtbl_cfg = + &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; + typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr = + &pgtbl_cfg->arm_lpae_s2_cfg.vtcr; + u64 vtcr_val; memset(target, 0, sizeof(*target)); @@ -1510,9 +1515,16 @@ static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, FIELD_PREP(STRTAB_STE_1_EATS, master->ats_enabled ? STRTAB_STE_1_EATS_TRANS : 0)); + vtcr_val = FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, vtcr->tsz) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, vtcr->sl) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, vtcr->irgn) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2OR0, vtcr->orgn) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2SH0, vtcr->sh) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | + FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); target->data[2] = cpu_to_le64( FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | - FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | + FIELD_PREP(STRTAB_STE_2_VTCR, vtcr_val) | STRTAB_STE_2_S2AA64 | #ifdef __BIG_ENDIAN STRTAB_STE_2_S2ENDI | @@ -1520,7 +1532,8 @@ static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2R); - target->data[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); + target->data[3] = cpu_to_le64(pgtbl_cfg->arm_lpae_s2_cfg.vttbr & + STRTAB_STE_3_S2TTB_MASK); } static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, @@ -2277,7 +2290,6 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, int vmid; struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; - typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr; /* Reserve VMID 0 for stage-2 bypass STEs */ vmid = ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, @@ -2285,16 +2297,7 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, if (vmid < 0) return vmid; - vtcr = &pgtbl_cfg->arm_lpae_s2_cfg.vtcr; cfg->vmid = (u16)vmid; - cfg->vttbr = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; - cfg->vtcr = FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, vtcr->tsz) | - FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, vtcr->sl) | - FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, vtcr->irgn) | - FIELD_PREP(STRTAB_STE_2_VTCR_S2OR0, vtcr->orgn) | - FIELD_PREP(STRTAB_STE_2_VTCR_S2SH0, vtcr->sh) | - FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | - FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); return 0; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 27ddf1acd12cea..1be0c1151c50c3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -609,8 +609,6 @@ struct arm_smmu_ctx_desc_cfg { struct arm_smmu_s2_cfg { u16 vmid; - u64 vttbr; - u64 vtcr; }; struct arm_smmu_strtab_cfg {
Half the code was living in arm_smmu_domain_finalise_s2(), just move it here and take the values directly from the pgtbl_ops instead of storing copies. Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 27 ++++++++++++--------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 -- 2 files changed, 15 insertions(+), 14 deletions(-)