diff mbox series

[net-next,v3,1/8] dt-bindings: net: Introduce the Qualcomm IPQESS Ethernet switch

Message ID 20231114105600.1012056-2-romain.gantois@bootlin.com (mailing list archive)
State Changes Requested
Delegated to: Netdev Maintainers
Headers show
Series net: qualcomm: ipqess: introduce Qualcomm IPQESS driver | expand

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Context Check Description
netdev/series_format success Posting correctly formatted
netdev/tree_selection success Clearly marked for net-next, async
netdev/fixes_present success Fixes tag not required for -next series
netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 8 this patch: 8
netdev/cc_maintainers warning 3 maintainers not CCed: konrad.dybcio@linaro.org conor+dt@kernel.org linux-arm-msm@vger.kernel.org
netdev/build_clang success Errors and warnings before: 8 this patch: 8
netdev/verify_signedoff success Signed-off-by tag matches author and committer
netdev/deprecated_api success None detected
netdev/check_selftest success No net selftest shell script
netdev/verify_fixes success No Fixes tag
netdev/build_allmodconfig_warn success Errors and warnings before: 8 this patch: 8
netdev/checkpatch warning WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
netdev/build_clang_rust success No Rust files in patch. Skipping build
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/source_inline success Was 0 now: 0

Commit Message

Romain Gantois Nov. 14, 2023, 10:55 a.m. UTC 
Add the DT binding for the IPQESS Ethernet switch subsystem, that
integrates a modified QCA8K switch and an EDMA MAC controller. It inherits
from a basic ethernet switch binding and adds three regmaps, a phandle and
reset line for the PSGMII, a phandle to the MDIO bus, a clock, and 32
interrupts.

Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
---
 .../bindings/net/qcom,ipq4019-ess.yaml        | 152 ++++++++++++++++++
 1 file changed, 152 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml

Comments

Krzysztof Kozlowski Nov. 16, 2023, 12:22 p.m. UTC | #1 
On 14/11/2023 11:55, Romain Gantois wrote:
> Add the DT binding for the IPQESS Ethernet switch subsystem, that
> integrates a modified QCA8K switch and an EDMA MAC controller. It inherits
> from a basic ethernet switch binding and adds three regmaps, a phandle and
> reset line for the PSGMII, a phandle to the MDIO bus, a clock, and 32
> interrupts.
> 
> Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
> ---
>  .../bindings/net/qcom,ipq4019-ess.yaml        | 152 ++++++++++++++++++
>  1 file changed, 152 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml
> new file mode 100644
> index 000000000000..85dff85e50b5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml
> @@ -0,0 +1,152 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/qcom,ipq4019-ess.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ4019 Ethernet Switch Subsystem
> +
> +maintainers:
> +  - Romain Gantois <romain.gantois@bootlin.com>
> +
> +$ref: ethernet-switch.yaml#
> +
> +properties:
> +  compatible:
> +    const: qcom,ipq4019-ess
> +
> +  reg:
> +    items:
> +      - description: Base ESS registers, which configure the integrated QCA8K switch.
> +      - description: ESS PSGMII-related registers, which control VCO calibration and link
> +                     modes.
> +      - description: ESS EDMA controller registers. The EDMA controller is an Ethernet
> +                     controller connected to the integrated switch's CPU port.

Blank line

> +  reg-names:
> +    items:
> +      - const: base
> +      - const: psgmii_phy
> +      - const: edma
> +
> +  resets:
> +    items:
> +      - description: Handle to the PSGMII reset line.

Don't describe Devicetree, so handle (assuming you speak about phandle)
is redundant, so:
PSGMII reset line

If it is some other handle, please explain.

But then isn't PSGMII reset property of MDIO or PHY? It looks like you
add here properties from the PHY...

> +      - description: Handle to the ESS reset line.

ESS reset line


> +
> +  reset-names:
> +    items:
> +      - const: psgmii
> +      - const: ess
> +
> +  clocks:
> +    maxItems: 1
> +    description: Handle to the GCC ESS clock

Drop description.

> +
> +  mdio:
> +    maxItems: 1
> +    description: Handle to the IPQ4019 MDIO Controller
> +
> +  interrupts:
> +    maxItems: 32
> +    description: One interrupt per tx and rx queue, the first 16 are rx queues
> +                 and the last 16 are the tx queues
> +

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml
new file mode 100644
index 000000000000..85dff85e50b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-ess.yaml
@@ -0,0 +1,152 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/qcom,ipq4019-ess.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ4019 Ethernet Switch Subsystem
+
+maintainers:
+  - Romain Gantois <romain.gantois@bootlin.com>
+
+$ref: ethernet-switch.yaml#
+
+properties:
+  compatible:
+    const: qcom,ipq4019-ess
+
+  reg:
+    items:
+      - description: Base ESS registers, which configure the integrated QCA8K switch.
+      - description: ESS PSGMII-related registers, which control VCO calibration and link
+                     modes.
+      - description: ESS EDMA controller registers. The EDMA controller is an Ethernet
+                     controller connected to the integrated switch's CPU port.
+  reg-names:
+    items:
+      - const: base
+      - const: psgmii_phy
+      - const: edma
+
+  resets:
+    items:
+      - description: Handle to the PSGMII reset line.
+      - description: Handle to the ESS reset line.
+
+  reset-names:
+    items:
+      - const: psgmii
+      - const: ess
+
+  clocks:
+    maxItems: 1
+    description: Handle to the GCC ESS clock
+
+  mdio:
+    maxItems: 1
+    description: Handle to the IPQ4019 MDIO Controller
+
+  interrupts:
+    maxItems: 32
+    description: One interrupt per tx and rx queue, the first 16 are rx queues
+                 and the last 16 are the tx queues
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - resets
+  - reset-names
+  - clocks
+  - mdio
+  - interrupts
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    switch: switch@c000000 {
+        compatible = "qcom,ipq4019-ess";
+        reg = <0xc000000 0x80000>, <0x98000 0x800>, <0xc080000 0x80000>;
+        reg-names = "base", "psgmii_phy", "edma";
+        resets = <&gcc ESS_PSGMII_ARES>, <&gcc ESS_RESET>;
+        reset-names = "psgmii", "ess";
+        clocks = <&gcc GCC_ESS_CLK>;
+        mdio = <&mdio>;
+        interrupts = <GIC_SPI  65 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  66 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  67 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  68 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  69 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  70 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  71 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  72 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  73 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  74 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  75 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  76 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  77 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  78 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  79 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI  80 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            swport1: port@1 { /* MAC1 */
+                 reg = <1>;
+                 label = "lan1";
+                 phy-handle = <&ethphy0>;
+                 phy-mode = "psgmii";
+            };
+
+            swport2: port@2 { /* MAC2 */
+                 reg = <2>;
+                 label = "lan2";
+                 phy-handle = <&ethphy1>;
+                 phy-mode = "psgmii";
+            };
+
+            swport3: port@3 { /* MAC3 */
+                 reg = <3>;
+                 label = "lan3";
+                 phy-handle = <&ethphy2>;
+                 phy-mode = "psgmii";
+            };
+
+            swport4: port@4 { /* MAC4 */
+                 reg = <4>;
+                 label = "lan4";
+                 phy-handle = <&ethphy3>;
+                 phy-mode = "psgmii";
+            };
+
+            swport5: port@5 { /* MAC5 */
+                 reg = <5>;
+                 label = "wan";
+                 phy-handle = <&ethphy4>;
+                 phy-mode = "psgmii";
+            };
+        };
+    };
+
+...