| Message ID | 1e5836360485b63e15bdf58da59e83139666b290.1699879741.git.unicorn_wang@outlook.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | riscv: sophgo: add clock support for sg2042 | expand |
On Mon, Nov 13, 2023 at 09:19:31PM +0800, Chen Wang wrote: > From: Chen Wang <unicorn_wang@outlook.com> > > Add bindings for the clock generator on the SG2042 RISC-V SoC. > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > --- > .../clock/sophgo/sophgo,sg2042-clkgen.yaml | 48 +++++++++++++++++++ > 1 file changed, 48 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml > > diff --git a/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml > new file mode 100644 > index 000000000000..e372d5dca5b9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo SG2042 Clock Generator > + > +maintainers: > + - Chen Wang <unicorn_wang@outlook.com> > + > +properties: > + compatible: > + const: sophgo,sg2042-clkgen > + > + system-ctrl: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to System Register Controller syscon node. > + description: > + The phandle to System Register Controller syscon node. Forget what I just said about syscon.yaml... You don't need a phandle here. Just make this node a child of the syscon. However, why do you need a child at all? Just add 'clocks' and '#clock-cells' to the parent directly. You don't need a child node when there's only 1 child node. Maybe there's other functions, but I have no visibility into that. IOW, define what all the functions are so we can provide better guidance. Rob
On 2023/11/17 2:18, Rob Herring wrote: > On Mon, Nov 13, 2023 at 09:19:31PM +0800, Chen Wang wrote: >> From: Chen Wang <unicorn_wang@outlook.com> >> >> Add bindings for the clock generator on the SG2042 RISC-V SoC. >> >> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> >> --- >> .../clock/sophgo/sophgo,sg2042-clkgen.yaml | 48 +++++++++++++++++++ >> 1 file changed, 48 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml >> >> diff --git a/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml >> new file mode 100644 >> index 000000000000..e372d5dca5b9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml >> @@ -0,0 +1,48 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Sophgo SG2042 Clock Generator >> + >> +maintainers: >> + - Chen Wang <unicorn_wang@outlook.com> >> + >> +properties: >> + compatible: >> + const: sophgo,sg2042-clkgen >> + >> + system-ctrl: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + items: >> + - items: >> + - description: phandle to System Register Controller syscon node. >> + description: >> + The phandle to System Register Controller syscon node. > Forget what I just said about syscon.yaml... > > You don't need a phandle here. Just make this node a child of the > syscon. Yes, making this node a child of syscon is a better solution and then we need not a phandle here. > However, why do you need a child at all? Just add 'clocks' and > '#clock-cells' to the parent directly. You don't need a child node when > there's only 1 child node. Maybe there's other functions, but I have no > visibility into that. IOW, define what all the functions are so we can > provide better guidance. The syscon is a module in SG2042 that provides multipile functions, and clock control is just one of them. I will add more other functions's nodes later under the syscon in coming patches, such as reset, pinctrl etc. > > Rob
diff --git a/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml new file mode 100644 index 000000000000..e372d5dca5b9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Clock Generator + +maintainers: + - Chen Wang <unicorn_wang@outlook.com> + +properties: + compatible: + const: sophgo,sg2042-clkgen + + system-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller syscon node. + description: + The phandle to System Register Controller syscon node. + + clocks: + items: + - description: Clock Generation IC (25 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo-sg2042-clk.h> for valid indices. + +required: + - compatible + - system-ctrl + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "sophgo,sg2042-clkgen"; + clocks = <&cgi>; + system-ctrl = <&sys_ctrl>; + #clock-cells = <1>; + };