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[0/4] clk: qcom: Introduce clocks drivers for SC8380XP

Message ID 20231025133320.4720-1-quic_sibis@quicinc.com (mailing list archive)
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Series clk: qcom: Introduce clocks drivers for SC8380XP | expand

Message

Sibi Sankar Oct. 25, 2023, 1:33 p.m. UTC 
This series adds initial clock support for the Qualcomm SC8380XP platform, aka Snapdragon X Elite.

Dependencies: None
Release Link: https://www.qualcomm.com/news/releases/2023/10/qualcomm-unleashes-snapdragon-x-elite--the-ai-super-charged-plat

Rajendra Nayak (4):
  dt-bindings: clock: qcom: Add SC8380XP GCC clocks
  clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP
  dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for SC8380XP
  clk: qcom: rpmh: Add support for SC8380XP rpmh clocks

 .../bindings/clock/qcom,rpmhcc.yaml           |    1 +
 .../bindings/clock/qcom,sc8380xp-gcc.yaml     |   72 +
 drivers/clk/qcom/Kconfig                      |   10 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/clk-rpmh.c                   |   26 +
 drivers/clk/qcom/gcc-sc8380xp.c               | 6812 +++++++++++++++++
 include/dt-bindings/clock/qcom,sc8380xp-gcc.h |  485 ++
 7 files changed, 7407 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8380xp-gcc.yaml
 create mode 100644 drivers/clk/qcom/gcc-sc8380xp.c
 create mode 100644 include/dt-bindings/clock/qcom,sc8380xp-gcc.h

Comments

Bryan O'Donoghue Oct. 25, 2023, 4:40 p.m. UTC | #1 
On 25/10/2023 14:33, Sibi Sankar wrote:
> From: Rajendra Nayak <quic_rjendra@quicinc.com>
> 
> Add support for the global clock controller found on SC8380XP
> based devices.
> 
> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---
>   drivers/clk/qcom/Kconfig        |   10 +
>   drivers/clk/qcom/Makefile       |    1 +
>   drivers/clk/qcom/gcc-sc8380xp.c | 6812 +++++++++++++++++++++++++++++++
>   3 files changed, 6823 insertions(+)
>   create mode 100644 drivers/clk/qcom/gcc-sc8380xp.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index ad1acd9b7426..013b3a1ad551 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -515,6 +515,16 @@ config SC_GCC_8280XP
>   	  Say Y if you want to use peripheral devices such as UART, SPI,
>   	  I2C, USB, UFS, SDCC, etc.
>   
> +config SC_GCC_8380XP
> +	tristate "SC8380XP Global Clock Controller"
> +	select QCOM_GDSC
> +	depends on COMMON_CLK_QCOM
> +	help
> +	  Support for the global clock controller on Qualcomm Technologies, Inc
> +	  SC8380XP devices.
> +	  Say Y if you want to use peripheral devices such as UART, SPI, I2C,
> +	  USB, UFS, SD/eMMC, PCIe, etc.
> +
>   config SC_GPUCC_7180
>   	tristate "SC7180 Graphics Clock Controller"
>   	depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 17edd73f9839..11b1f79e15c5 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -77,6 +77,7 @@ obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
>   obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o
>   obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o
>   obj-$(CONFIG_SC_GCC_8280XP) += gcc-sc8280xp.o
> +obj-$(CONFIG_SC_GCC_8380XP) += gcc-sc8380xp.o
>   obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
>   obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o
>   obj-$(CONFIG_SC_GPUCC_8280XP) += gpucc-sc8280xp.o
> diff --git a/drivers/clk/qcom/gcc-sc8380xp.c b/drivers/clk/qcom/gcc-sc8380xp.c
> new file mode 100644
> index 000000000000..48c50f9421c8
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-sc8380xp.c
> @@ -0,0 +1,6812 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,sc8380xp-gcc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "clk-regmap-phy-mux.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> +	DT_BI_TCXO,
> +	DT_SLEEP_CLK,
> +	DT_PCIE_3_PIPE,
> +	DT_PCIE_4_PIPE,
> +	DT_PCIE_5_PIPE,
> +	DT_PCIE_6A_PIPE,
> +	DT_PCIE_6B_PIPE,
> +	DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,
> +	DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,
> +	DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,
> +};
> +
> +enum {
> +	P_BI_TCXO,
> +	P_GCC_GPLL0_OUT_EVEN,
> +	P_GCC_GPLL0_OUT_MAIN,
> +	P_GCC_GPLL4_OUT_MAIN,
> +	P_GCC_GPLL7_OUT_MAIN,
> +	P_GCC_GPLL8_OUT_MAIN,
> +	P_GCC_GPLL9_OUT_MAIN,
> +	P_SLEEP_CLK,
> +	P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
> +	P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
> +	P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
> +};
> +
> +static struct clk_alpha_pll gcc_gpll0 = {
> +	.offset = 0x0,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> +	.clkr = {
> +		.enable_reg = 0x52030,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_gpll0",
> +			.parent_data = &(const struct clk_parent_data) {
> +				.index = DT_BI_TCXO,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
> +		},
> +	},
> +};
> +
> +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
> +	{ 0x1, 2 },
> +	{ }
> +};
> +
> +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
> +	.offset = 0x0,
> +	.post_div_shift = 10,
> +	.post_div_table = post_div_table_gcc_gpll0_out_even,
> +	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
> +	.width = 4,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_gpll0_out_even",
> +		.parent_hws = (const struct clk_hw*[]) {
> +			&gcc_gpll0.clkr.hw,
> +		},
> +		.num_parents = 1,
> +		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
> +	},
> +};
> +
> +static struct clk_alpha_pll gcc_gpll4 = {
> +	.offset = 0x4000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> +	.clkr = {
> +		.enable_reg = 0x52030,
> +		.enable_mask = BIT(4),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_gpll4",
> +			.parent_data = &(const struct clk_parent_data) {
> +				.index = DT_BI_TCXO,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_alpha_pll gcc_gpll7 = {
> +	.offset = 0x7000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> +	.clkr = {
> +		.enable_reg = 0x52030,
> +		.enable_mask = BIT(7),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_gpll7",
> +			.parent_data = &(const struct clk_parent_data) {
> +				.index = DT_BI_TCXO,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_alpha_pll gcc_gpll8 = {
> +	.offset = 0x8000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> +	.clkr = {
> +		.enable_reg = 0x52030,
> +		.enable_mask = BIT(8),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_gpll8",
> +			.parent_data = &(const struct clk_parent_data) {
> +				.index = DT_BI_TCXO,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_alpha_pll gcc_gpll9 = {
> +	.offset = 0x9000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> +	.clkr = {
> +		.enable_reg = 0x52030,
> +		.enable_mask = BIT(9),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_gpll9",
> +			.parent_data = &(const struct clk_parent_data) {
> +				.index = DT_BI_TCXO,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
> +		},
> +	},
> +};
> +
> +static const struct parent_map gcc_parent_map_0[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_GCC_GPLL0_OUT_MAIN, 1 },
> +	{ P_GCC_GPLL0_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_0[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &gcc_gpll0.clkr.hw },
> +	{ .hw = &gcc_gpll0_out_even.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_1[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_SLEEP_CLK, 5 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_1[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .index = DT_SLEEP_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_2[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_GCC_GPLL0_OUT_MAIN, 1 },
> +	{ P_SLEEP_CLK, 5 },
> +	{ P_GCC_GPLL0_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_2[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &gcc_gpll0.clkr.hw },
> +	{ .index = DT_SLEEP_CLK },
> +	{ .hw = &gcc_gpll0_out_even.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_3[] = {
> +	{ P_BI_TCXO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_3[] = {
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_4[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_GCC_GPLL0_OUT_MAIN, 1 },
> +	{ P_GCC_GPLL8_OUT_MAIN, 2 },
> +	{ P_GCC_GPLL0_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_4[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &gcc_gpll0.clkr.hw },
> +	{ .hw = &gcc_gpll8.clkr.hw },
> +	{ .hw = &gcc_gpll0_out_even.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_5[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_GCC_GPLL0_OUT_MAIN, 1 },
> +	{ P_GCC_GPLL7_OUT_MAIN, 2 },
> +	{ P_SLEEP_CLK, 5 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_5[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &gcc_gpll0.clkr.hw },
> +	{ .hw = &gcc_gpll7.clkr.hw },
> +	{ .index = DT_SLEEP_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_6[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_GCC_GPLL0_OUT_MAIN, 1 },
> +	{ P_GCC_GPLL7_OUT_MAIN, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_6[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &gcc_gpll0.clkr.hw },
> +	{ .hw = &gcc_gpll7.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_7[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_GCC_GPLL0_OUT_MAIN, 1 },
> +	{ P_GCC_GPLL4_OUT_MAIN, 5 },
> +	{ P_GCC_GPLL0_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_7[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &gcc_gpll0.clkr.hw },
> +	{ .hw = &gcc_gpll4.clkr.hw },
> +	{ .hw = &gcc_gpll0_out_even.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_8[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_GCC_GPLL0_OUT_MAIN, 1 },
> +	{ P_GCC_GPLL7_OUT_MAIN, 2 },
> +	{ P_GCC_GPLL0_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_8[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &gcc_gpll0.clkr.hw },
> +	{ .hw = &gcc_gpll7.clkr.hw },
> +	{ .hw = &gcc_gpll0_out_even.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_9[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_GCC_GPLL0_OUT_MAIN, 1 },
> +	{ P_GCC_GPLL9_OUT_MAIN, 2 },
> +	{ P_GCC_GPLL4_OUT_MAIN, 5 },
> +	{ P_GCC_GPLL0_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_10[] = {
> +	{ .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_10[] = {
> +	{ P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_11[] = {
> +	{ .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_11[] = {
> +	{ P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_12[] = {
> +	{ .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_12[] = {
> +	{ P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_9[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &gcc_gpll0.clkr.hw },
> +	{ .hw = &gcc_gpll9.clkr.hw },
> +	{ .hw = &gcc_gpll4.clkr.hw },
> +	{ .hw = &gcc_gpll0_out_even.clkr.hw },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
> +	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
> +	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
> +	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_gp1_clk_src = {
> +	.cmd_rcgr = 0x64004,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_2,
> +	.freq_tbl = ftbl_gcc_gp1_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_gp1_clk_src",
> +		.parent_data = gcc_parent_data_2,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_gp2_clk_src = {
> +	.cmd_rcgr = 0x65004,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_2,
> +	.freq_tbl = ftbl_gcc_gp1_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_gp2_clk_src",
> +		.parent_data = gcc_parent_data_2,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_gp3_clk_src = {
> +	.cmd_rcgr = 0x66004,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_2,
> +	.freq_tbl = ftbl_gcc_gp1_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_gp3_clk_src",
> +		.parent_data = gcc_parent_data_2,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
> +	F(19200000, P_BI_TCXO, 1, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
> +	.cmd_rcgr = 0xa0180,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_1,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_0_aux_clk_src",
> +		.parent_data = gcc_parent_data_1,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
> +	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
> +	.cmd_rcgr = 0xa0054,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_0_phy_rchng_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
> +	.cmd_rcgr = 0x2c180,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_1,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_1_aux_clk_src",
> +		.parent_data = gcc_parent_data_1,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
> +	.cmd_rcgr = 0x2c054,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_1_phy_rchng_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
> +	.cmd_rcgr = 0x13180,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_1,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_2_aux_clk_src",
> +		.parent_data = gcc_parent_data_1,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {
> +	.cmd_rcgr = 0x13054,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_2_phy_rchng_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {
> +	.cmd_rcgr = 0x5808c,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_1,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_3_aux_clk_src",
> +		.parent_data = gcc_parent_data_1,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = {
> +	.cmd_rcgr = 0x58070,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_3_phy_rchng_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {
> +	.cmd_rcgr = 0x6b080,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_1,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_4_aux_clk_src",
> +		.parent_data = gcc_parent_data_1,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {
> +	.cmd_rcgr = 0x6b064,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_4_phy_rchng_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_5_aux_clk_src = {
> +	.cmd_rcgr = 0x2f080,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_1,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_5_aux_clk_src",
> +		.parent_data = gcc_parent_data_1,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = {
> +	.cmd_rcgr = 0x2f064,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_5_phy_rchng_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = {
> +	.cmd_rcgr = 0x3108c,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_1,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_6a_aux_clk_src",
> +		.parent_data = gcc_parent_data_1,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = {
> +	.cmd_rcgr = 0x31070,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_6a_phy_rchng_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = {
> +	.cmd_rcgr = 0x8d08c,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_1,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_6b_aux_clk_src",
> +		.parent_data = gcc_parent_data_1,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = {
> +	.cmd_rcgr = 0x8d070,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_6b_phy_rchng_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = {
> +	.cmd_rcgr = 0xa400c,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_3,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pcie_rscc_xo_clk_src",
> +		.parent_data = gcc_parent_data_3,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
> +	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_pdm2_clk_src = {
> +	.cmd_rcgr = 0x33010,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pdm2_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_pdm2_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,

Again difference to sc8280xp - should this be clk_rcg2_shared_ops to park ?

> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
> +	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
> +	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
> +	F(19200000, P_BI_TCXO, 1, 0, 0),
> +	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
> +	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
> +	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
> +	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
> +	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
> +	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
> +	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
> +	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
> +	.name = "gcc_qupv3_wrap0_s0_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,

Shared on sc8280xp - should be shared on sc8380xp ? Same comment for all 
of the qupv3 .ops.

> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
> +	.cmd_rcgr = 0x42010,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
> +	.name = "gcc_qupv3_wrap0_s1_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
> +	.cmd_rcgr = 0x42148,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
> +	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
> +	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
> +	F(19200000, P_BI_TCXO, 1, 0, 0),
> +	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
> +	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
> +	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
> +	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
> +	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
> +	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
> +	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
> +	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
> +	.name = "gcc_qupv3_wrap0_s2_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
> +	.cmd_rcgr = 0x42288,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
> +	.name = "gcc_qupv3_wrap0_s3_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
> +	.cmd_rcgr = 0x423c8,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
> +	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
> +	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
> +	F(19200000, P_BI_TCXO, 1, 0, 0),
> +	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
> +	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
> +	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
> +	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
> +	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
> +	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
> +	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
> +	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
> +	.name = "gcc_qupv3_wrap0_s4_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
> +	.cmd_rcgr = 0x42500,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
> +	.name = "gcc_qupv3_wrap0_s5_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
> +	.cmd_rcgr = 0x42638,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
> +	.name = "gcc_qupv3_wrap0_s6_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
> +	.cmd_rcgr = 0x42770,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
> +	.name = "gcc_qupv3_wrap0_s7_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
> +	.cmd_rcgr = 0x428a8,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
> +	.name = "gcc_qupv3_wrap1_s0_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
> +	.cmd_rcgr = 0x18010,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
> +	.name = "gcc_qupv3_wrap1_s1_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
> +	.cmd_rcgr = 0x18148,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
> +	.name = "gcc_qupv3_wrap1_s2_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
> +	.cmd_rcgr = 0x18288,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
> +	.name = "gcc_qupv3_wrap1_s3_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
> +	.cmd_rcgr = 0x183c8,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
> +	.name = "gcc_qupv3_wrap1_s4_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
> +	.cmd_rcgr = 0x18500,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
> +	.name = "gcc_qupv3_wrap1_s5_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
> +	.cmd_rcgr = 0x18638,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
> +	.name = "gcc_qupv3_wrap1_s6_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
> +	.cmd_rcgr = 0x18770,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
> +	.name = "gcc_qupv3_wrap1_s7_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
> +	.cmd_rcgr = 0x188a8,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
> +	.name = "gcc_qupv3_wrap2_s0_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
> +	.cmd_rcgr = 0x1e010,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
> +	.name = "gcc_qupv3_wrap2_s1_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
> +	.cmd_rcgr = 0x1e148,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
> +	.name = "gcc_qupv3_wrap2_s2_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
> +	.cmd_rcgr = 0x1e288,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
> +	.name = "gcc_qupv3_wrap2_s3_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
> +	.cmd_rcgr = 0x1e3c8,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
> +	.name = "gcc_qupv3_wrap2_s4_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
> +	.cmd_rcgr = 0x1e500,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
> +	.name = "gcc_qupv3_wrap2_s5_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
> +	.cmd_rcgr = 0x1e638,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
> +	.name = "gcc_qupv3_wrap2_s6_clk_src",
> +	.parent_data = gcc_parent_data_8,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
> +	.cmd_rcgr = 0x1e770,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_8,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
> +	.name = "gcc_qupv3_wrap2_s7_clk_src",
> +	.parent_data = gcc_parent_data_0,
> +	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +	.flags = CLK_SET_RATE_PARENT,
> +	.ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
> +	.cmd_rcgr = 0x1e8a8,
> +	.mnd_width = 16,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
> +	.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> +	F(400000, P_BI_TCXO, 12, 1, 4),
> +	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> +	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
> +	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> +	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
> +	.cmd_rcgr = 0x14018,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_9,
> +	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_sdcc2_apps_clk_src",
> +		.parent_data = gcc_parent_data_9,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_floor_ops,

diff sc8280xp..sc8380xp

Here you've used floor instead of shared ops, why is that ?

> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
> +	F(400000, P_BI_TCXO, 12, 1, 4),
> +	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> +	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
> +	.cmd_rcgr = 0x16018,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_sdcc4_apps_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_floor_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
> +	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> +	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
> +	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
> +	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
> +	.cmd_rcgr = 0x77030,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_ufs_phy_axi_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,

This looks correct since you want to persist this clock in suspend 
presumably.

> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
> +	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> +	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
> +	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
> +	.cmd_rcgr = 0x77080,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_7,
> +	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_ufs_phy_ice_core_clk_src",
> +		.parent_data = gcc_parent_data_7,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
> +	.cmd_rcgr = 0x770b4,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_3,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_ufs_phy_phy_aux_clk_src",
> +		.parent_data = gcc_parent_data_3,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,

but then why not ufs_phy_ice_core and ufs_phy_phy_aux_clk

> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
> +	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
> +	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
> +	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
> +	.cmd_rcgr = 0x77098,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_ufs_phy_unipro_core_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,

but back to the parked clock here.

Shoudln't all of the UFS related clocks park in suspend ?

> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
> +	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
> +	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_usb20_master_clk_src = {
> +	.cmd_rcgr = 0x2902c,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_usb20_master_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_usb20_master_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
> +	.cmd_rcgr = 0x29158,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_usb20_mock_utmi_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
> +	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
> +	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
> +	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
> +	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
> +	.cmd_rcgr = 0x1702c,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_usb30_mp_master_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_shared_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
> +	.cmd_rcgr = 0x17158,
> +	.mnd_width = 0,
> +	.hid_width = 5,
> +	.parent_map = gcc_parent_map_0,
> +	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_usb30_mp_mock_utmi_clk_src",
> +		.parent_data = gcc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_rcg2_ops,

This is another discontinuinty with sc8280xp.

Could you have a look through the sc8280xp gcc and do an aduit for 
clk_rcg2_shared_ops as against sc8380xp ?

---
bod
Konrad Dybcio Oct. 26, 2023, 11:06 a.m. UTC | #2 
On 10/25/23 15:33, Sibi Sankar wrote:
> From: Rajendra Nayak <quic_rjendra@quicinc.com>
> 
> Add support for the global clock controller found on SC8380XP
> based devices.
> 
> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---
[...]

> +static int gcc_sc8380xp_probe(struct platform_device *pdev)
> +{
> +	struct regmap *regmap;
> +	int ret;
> +
> +	regmap = qcom_cc_map(pdev, &gcc_sc8380xp_desc);
> +	if (IS_ERR(regmap))
> +		return PTR_ERR(regmap);
> +
> +	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> +				       ARRAY_SIZE(gcc_dfs_clocks));
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Keep the critical clock always-On
> +	 * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
> +	 * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
> +	 * gcc_video_xo_clk
> +	 */
> +	regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
Please inline the clock names, like so:

regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */

LGTM otherwise

Konrad
Krzysztof Kozlowski Oct. 27, 2023, 8:21 a.m. UTC | #3 
On 25/10/2023 15:33, Sibi Sankar wrote:
> From: Rajendra Nayak <quic_rjendra@quicinc.com>
> 
> Add support for the global clock controller found on SC8380XP
> based devices.
> 
> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---
>  drivers/clk/qcom/Kconfig        |   10 +
>  drivers/clk/qcom/Makefile       |    1 +
>  drivers/clk/qcom/gcc-sc8380xp.c | 6812 +++++++++++++++++++++++++++++++
>  3 files changed, 6823 insertions(+)
>  create mode 100644 drivers/clk/qcom/gcc-sc8380xp.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index ad1acd9b7426..013b3a1ad551 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -515,6 +515,16 @@ config SC_GCC_8280XP
>  	  Say Y if you want to use peripheral devices such as UART, SPI,
>  	  I2C, USB, UFS, SDCC, etc.
>  
> +config SC_GCC_8380XP
> +	tristate "SC8380XP Global Clock Controller"
> +	select QCOM_GDSC
> +	depends on COMMON_CLK_QCOM

Please stgart any new work starting from some driver in linux-next. You
would not make the same mistakes we fixed recently.

depends on ARM64 || COMPILE_TEST

Best regards,
Krzysztof
Sibi Sankar Nov. 17, 2023, 3:56 a.m. UTC | #4 
Hey Bryan,

Thanks for taking time to review the series.

On 10/25/23 22:10, Bryan O'Donoghue wrote:
> On 25/10/2023 14:33, Sibi Sankar wrote:
>> From: Rajendra Nayak <quic_rjendra@quicinc.com>
>>
>> Add support for the global clock controller found on SC8380XP
>> based devices.
>>
>> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
>> ---
>>   drivers/clk/qcom/Kconfig        |   10 +
>>   drivers/clk/qcom/Makefile       |    1 +
>>   drivers/clk/qcom/gcc-sc8380xp.c | 6812 +++++++++++++++++++++++++++++++
>>   3 files changed, 6823 insertions(+)
>>   create mode 100644 drivers/clk/qcom/gcc-sc8380xp.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index ad1acd9b7426..013b3a1ad551 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -515,6 +515,16 @@ config SC_GCC_8280XP
>>         Say Y if you want to use peripheral devices such as UART, SPI,
>>         I2C, USB, UFS, SDCC, etc.
>> +config SC_GCC_8380XP
>> +    tristate "SC8380XP Global Clock Controller"
>> +    select QCOM_GDSC
>> +    depends on COMMON_CLK_QCOM
>> +    help
>> +      Support for the global clock controller on Qualcomm 
>> Technologies, Inc
>> +      SC8380XP devices.
>> +      Say Y if you want to use peripheral devices such as UART, SPI, 
>> I2C,
>> +      USB, UFS, SD/eMMC, PCIe, etc.
>> +
>>   config SC_GPUCC_7180
>>       tristate "SC7180 Graphics Clock Controller"
>>       depends on ARM64 || COMPILE_TEST
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index 17edd73f9839..11b1f79e15c5 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -77,6 +77,7 @@ obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
>>   obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o
>>   obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o
>>   obj-$(CONFIG_SC_GCC_8280XP) += gcc-sc8280xp.o
>> +obj-$(CONFIG_SC_GCC_8380XP) += gcc-sc8380xp.o
>>   obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
>>   obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o
>>   obj-$(CONFIG_SC_GPUCC_8280XP) += gpucc-sc8280xp.o
>> diff --git a/drivers/clk/qcom/gcc-sc8380xp.c 
>> b/drivers/clk/qcom/gcc-sc8380xp.c
>> new file mode 100644
>> index 000000000000..48c50f9421c8
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-sc8380xp.c
>> @@ -0,0 +1,6812 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights 
>> reserved.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <dt-bindings/clock/qcom,sc8380xp-gcc.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "clk-regmap-phy-mux.h"
>> +#include "gdsc.h"
>> +#include "reset.h"
>> +
>> +enum {
>> +    DT_BI_TCXO,
>> +    DT_SLEEP_CLK,
>> +    DT_PCIE_3_PIPE,
>> +    DT_PCIE_4_PIPE,
>> +    DT_PCIE_5_PIPE,
>> +    DT_PCIE_6A_PIPE,
>> +    DT_PCIE_6B_PIPE,
>> +    DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,
>> +    DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,
>> +    DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,
>> +};
>> +
>> +enum {
>> +    P_BI_TCXO,
>> +    P_GCC_GPLL0_OUT_EVEN,
>> +    P_GCC_GPLL0_OUT_MAIN,
>> +    P_GCC_GPLL4_OUT_MAIN,
>> +    P_GCC_GPLL7_OUT_MAIN,
>> +    P_GCC_GPLL8_OUT_MAIN,
>> +    P_GCC_GPLL9_OUT_MAIN,
>> +    P_SLEEP_CLK,
>> +    P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
>> +    P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
>> +    P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
>> +};
>> +
>> +static struct clk_alpha_pll gcc_gpll0 = {
>> +    .offset = 0x0,
>> +    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> +    .clkr = {
>> +        .enable_reg = 0x52030,
>> +        .enable_mask = BIT(0),
>> +        .hw.init = &(const struct clk_init_data) {
>> +            .name = "gcc_gpll0",
>> +            .parent_data = &(const struct clk_parent_data) {
>> +                .index = DT_BI_TCXO,
>> +            },
>> +            .num_parents = 1,
>> +            .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
>> +        },
>> +    },
>> +};
>> +
>> +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] 
>> = {
>> +    { 0x1, 2 },
>> +    { }
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
>> +    .offset = 0x0,
>> +    .post_div_shift = 10,
>> +    .post_div_table = post_div_table_gcc_gpll0_out_even,
>> +    .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
>> +    .width = 4,
>> +    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_gpll0_out_even",
>> +        .parent_hws = (const struct clk_hw*[]) {
>> +            &gcc_gpll0.clkr.hw,
>> +        },
>> +        .num_parents = 1,
>> +        .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
>> +    },
>> +};
>> +
>> +static struct clk_alpha_pll gcc_gpll4 = {
>> +    .offset = 0x4000,
>> +    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> +    .clkr = {
>> +        .enable_reg = 0x52030,
>> +        .enable_mask = BIT(4),
>> +        .hw.init = &(const struct clk_init_data) {
>> +            .name = "gcc_gpll4",
>> +            .parent_data = &(const struct clk_parent_data) {
>> +                .index = DT_BI_TCXO,
>> +            },
>> +            .num_parents = 1,
>> +            .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
>> +        },
>> +    },
>> +};
>> +
>> +static struct clk_alpha_pll gcc_gpll7 = {
>> +    .offset = 0x7000,
>> +    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> +    .clkr = {
>> +        .enable_reg = 0x52030,
>> +        .enable_mask = BIT(7),
>> +        .hw.init = &(const struct clk_init_data) {
>> +            .name = "gcc_gpll7",
>> +            .parent_data = &(const struct clk_parent_data) {
>> +                .index = DT_BI_TCXO,
>> +            },
>> +            .num_parents = 1,
>> +            .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
>> +        },
>> +    },
>> +};
>> +
>> +static struct clk_alpha_pll gcc_gpll8 = {
>> +    .offset = 0x8000,
>> +    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> +    .clkr = {
>> +        .enable_reg = 0x52030,
>> +        .enable_mask = BIT(8),
>> +        .hw.init = &(const struct clk_init_data) {
>> +            .name = "gcc_gpll8",
>> +            .parent_data = &(const struct clk_parent_data) {
>> +                .index = DT_BI_TCXO,
>> +            },
>> +            .num_parents = 1,
>> +            .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
>> +        },
>> +    },
>> +};
>> +
>> +static struct clk_alpha_pll gcc_gpll9 = {
>> +    .offset = 0x9000,
>> +    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> +    .clkr = {
>> +        .enable_reg = 0x52030,
>> +        .enable_mask = BIT(9),
>> +        .hw.init = &(const struct clk_init_data) {
>> +            .name = "gcc_gpll9",
>> +            .parent_data = &(const struct clk_parent_data) {
>> +                .index = DT_BI_TCXO,
>> +            },
>> +            .num_parents = 1,
>> +            .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
>> +        },
>> +    },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_0[] = {
>> +    { P_BI_TCXO, 0 },
>> +    { P_GCC_GPLL0_OUT_MAIN, 1 },
>> +    { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_0[] = {
>> +    { .index = DT_BI_TCXO },
>> +    { .hw = &gcc_gpll0.clkr.hw },
>> +    { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_1[] = {
>> +    { P_BI_TCXO, 0 },
>> +    { P_SLEEP_CLK, 5 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_1[] = {
>> +    { .index = DT_BI_TCXO },
>> +    { .index = DT_SLEEP_CLK },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_2[] = {
>> +    { P_BI_TCXO, 0 },
>> +    { P_GCC_GPLL0_OUT_MAIN, 1 },
>> +    { P_SLEEP_CLK, 5 },
>> +    { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_2[] = {
>> +    { .index = DT_BI_TCXO },
>> +    { .hw = &gcc_gpll0.clkr.hw },
>> +    { .index = DT_SLEEP_CLK },
>> +    { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_3[] = {
>> +    { P_BI_TCXO, 0 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_3[] = {
>> +    { .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_4[] = {
>> +    { P_BI_TCXO, 0 },
>> +    { P_GCC_GPLL0_OUT_MAIN, 1 },
>> +    { P_GCC_GPLL8_OUT_MAIN, 2 },
>> +    { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_4[] = {
>> +    { .index = DT_BI_TCXO },
>> +    { .hw = &gcc_gpll0.clkr.hw },
>> +    { .hw = &gcc_gpll8.clkr.hw },
>> +    { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_5[] = {
>> +    { P_BI_TCXO, 0 },
>> +    { P_GCC_GPLL0_OUT_MAIN, 1 },
>> +    { P_GCC_GPLL7_OUT_MAIN, 2 },
>> +    { P_SLEEP_CLK, 5 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_5[] = {
>> +    { .index = DT_BI_TCXO },
>> +    { .hw = &gcc_gpll0.clkr.hw },
>> +    { .hw = &gcc_gpll7.clkr.hw },
>> +    { .index = DT_SLEEP_CLK },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_6[] = {
>> +    { P_BI_TCXO, 0 },
>> +    { P_GCC_GPLL0_OUT_MAIN, 1 },
>> +    { P_GCC_GPLL7_OUT_MAIN, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_6[] = {
>> +    { .index = DT_BI_TCXO },
>> +    { .hw = &gcc_gpll0.clkr.hw },
>> +    { .hw = &gcc_gpll7.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_7[] = {
>> +    { P_BI_TCXO, 0 },
>> +    { P_GCC_GPLL0_OUT_MAIN, 1 },
>> +    { P_GCC_GPLL4_OUT_MAIN, 5 },
>> +    { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_7[] = {
>> +    { .index = DT_BI_TCXO },
>> +    { .hw = &gcc_gpll0.clkr.hw },
>> +    { .hw = &gcc_gpll4.clkr.hw },
>> +    { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_8[] = {
>> +    { P_BI_TCXO, 0 },
>> +    { P_GCC_GPLL0_OUT_MAIN, 1 },
>> +    { P_GCC_GPLL7_OUT_MAIN, 2 },
>> +    { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_8[] = {
>> +    { .index = DT_BI_TCXO },
>> +    { .hw = &gcc_gpll0.clkr.hw },
>> +    { .hw = &gcc_gpll7.clkr.hw },
>> +    { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_9[] = {
>> +    { P_BI_TCXO, 0 },
>> +    { P_GCC_GPLL0_OUT_MAIN, 1 },
>> +    { P_GCC_GPLL9_OUT_MAIN, 2 },
>> +    { P_GCC_GPLL4_OUT_MAIN, 5 },
>> +    { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_10[] = {
>> +    { .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE },
>> +    { .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_10[] = {
>> +    { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
>> +    { P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_11[] = {
>> +    { .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE },
>> +    { .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_11[] = {
>> +    { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
>> +    { P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_12[] = {
>> +    { .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE },
>> +    { .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_12[] = {
>> +    { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
>> +    { P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_9[] = {
>> +    { .index = DT_BI_TCXO },
>> +    { .hw = &gcc_gpll0.clkr.hw },
>> +    { .hw = &gcc_gpll9.clkr.hw },
>> +    { .hw = &gcc_gpll4.clkr.hw },
>> +    { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
>> +    F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
>> +    F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
>> +    F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp1_clk_src = {
>> +    .cmd_rcgr = 0x64004,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_2,
>> +    .freq_tbl = ftbl_gcc_gp1_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_gp1_clk_src",
>> +        .parent_data = gcc_parent_data_2,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp2_clk_src = {
>> +    .cmd_rcgr = 0x65004,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_2,
>> +    .freq_tbl = ftbl_gcc_gp1_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_gp2_clk_src",
>> +        .parent_data = gcc_parent_data_2,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp3_clk_src = {
>> +    .cmd_rcgr = 0x66004,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_2,
>> +    .freq_tbl = ftbl_gcc_gp1_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_gp3_clk_src",
>> +        .parent_data = gcc_parent_data_2,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
>> +    F(19200000, P_BI_TCXO, 1, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
>> +    .cmd_rcgr = 0xa0180,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_1,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_0_aux_clk_src",
>> +        .parent_data = gcc_parent_data_1,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
>> +    F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
>> +    .cmd_rcgr = 0xa0054,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_0_phy_rchng_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
>> +    .cmd_rcgr = 0x2c180,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_1,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_1_aux_clk_src",
>> +        .parent_data = gcc_parent_data_1,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
>> +    .cmd_rcgr = 0x2c054,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_1_phy_rchng_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
>> +    .cmd_rcgr = 0x13180,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_1,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_2_aux_clk_src",
>> +        .parent_data = gcc_parent_data_1,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {
>> +    .cmd_rcgr = 0x13054,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_2_phy_rchng_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {
>> +    .cmd_rcgr = 0x5808c,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_1,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_3_aux_clk_src",
>> +        .parent_data = gcc_parent_data_1,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = {
>> +    .cmd_rcgr = 0x58070,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_3_phy_rchng_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {
>> +    .cmd_rcgr = 0x6b080,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_1,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_4_aux_clk_src",
>> +        .parent_data = gcc_parent_data_1,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {
>> +    .cmd_rcgr = 0x6b064,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_4_phy_rchng_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_5_aux_clk_src = {
>> +    .cmd_rcgr = 0x2f080,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_1,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_5_aux_clk_src",
>> +        .parent_data = gcc_parent_data_1,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = {
>> +    .cmd_rcgr = 0x2f064,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_5_phy_rchng_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = {
>> +    .cmd_rcgr = 0x3108c,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_1,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_6a_aux_clk_src",
>> +        .parent_data = gcc_parent_data_1,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = {
>> +    .cmd_rcgr = 0x31070,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_6a_phy_rchng_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = {
>> +    .cmd_rcgr = 0x8d08c,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_1,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_6b_aux_clk_src",
>> +        .parent_data = gcc_parent_data_1,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = {
>> +    .cmd_rcgr = 0x8d070,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_6b_phy_rchng_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = {
>> +    .cmd_rcgr = 0xa400c,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_3,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pcie_rscc_xo_clk_src",
>> +        .parent_data = gcc_parent_data_3,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_3),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
>> +    F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_pdm2_clk_src = {
>> +    .cmd_rcgr = 0x33010,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pdm2_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_pdm2_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
> 
> Again difference to sc8280xp - should this be clk_rcg2_shared_ops to park ?
> 
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
>> +    F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
>> +    F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
>> +    F(19200000, P_BI_TCXO, 1, 0, 0),
>> +    F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
>> +    F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
>> +    F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
>> +    F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
>> +    F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> +    F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
>> +    F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
>> +    F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap0_s0_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
> 
> Shared on sc8280xp - should be shared on sc8380xp ? Same comment for all 
> of the qupv3 .ops.
> 
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
>> +    .cmd_rcgr = 0x42010,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap0_s1_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
>> +    .cmd_rcgr = 0x42148,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
>> +    F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
>> +    F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
>> +    F(19200000, P_BI_TCXO, 1, 0, 0),
>> +    F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
>> +    F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
>> +    F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
>> +    F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
>> +    F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
>> +    F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
>> +    F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
>> +    F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap0_s2_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
>> +    .cmd_rcgr = 0x42288,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap0_s3_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
>> +    .cmd_rcgr = 0x423c8,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
>> +    F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
>> +    F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
>> +    F(19200000, P_BI_TCXO, 1, 0, 0),
>> +    F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
>> +    F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
>> +    F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
>> +    F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
>> +    F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> +    F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
>> +    F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
>> +    F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap0_s4_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
>> +    .cmd_rcgr = 0x42500,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap0_s5_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
>> +    .cmd_rcgr = 0x42638,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap0_s6_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
>> +    .cmd_rcgr = 0x42770,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap0_s7_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
>> +    .cmd_rcgr = 0x428a8,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap1_s0_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
>> +    .cmd_rcgr = 0x18010,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap1_s1_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
>> +    .cmd_rcgr = 0x18148,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap1_s2_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
>> +    .cmd_rcgr = 0x18288,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap1_s3_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
>> +    .cmd_rcgr = 0x183c8,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap1_s4_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
>> +    .cmd_rcgr = 0x18500,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap1_s5_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
>> +    .cmd_rcgr = 0x18638,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap1_s6_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
>> +    .cmd_rcgr = 0x18770,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap1_s7_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
>> +    .cmd_rcgr = 0x188a8,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap2_s0_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
>> +    .cmd_rcgr = 0x1e010,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap2_s1_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
>> +    .cmd_rcgr = 0x1e148,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap2_s2_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
>> +    .cmd_rcgr = 0x1e288,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap2_s3_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
>> +    .cmd_rcgr = 0x1e3c8,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap2_s4_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
>> +    .cmd_rcgr = 0x1e500,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap2_s5_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
>> +    .cmd_rcgr = 0x1e638,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap2_s6_clk_src",
>> +    .parent_data = gcc_parent_data_8,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_8),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
>> +    .cmd_rcgr = 0x1e770,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_8,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
>> +    .name = "gcc_qupv3_wrap2_s7_clk_src",
>> +    .parent_data = gcc_parent_data_0,
>> +    .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +    .flags = CLK_SET_RATE_PARENT,
>> +    .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
>> +    .cmd_rcgr = 0x1e8a8,
>> +    .mnd_width = 16,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
>> +    .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
>> +    F(400000, P_BI_TCXO, 12, 1, 4),
>> +    F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
>> +    F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
>> +    F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
>> +    F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
>> +    .cmd_rcgr = 0x14018,
>> +    .mnd_width = 8,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_9,
>> +    .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_sdcc2_apps_clk_src",
>> +        .parent_data = gcc_parent_data_9,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_9),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_floor_ops,
> 
> diff sc8280xp..sc8380xp
> 
> Here you've used floor instead of shared ops, why is that ?

We seem to use floor ops for sdcc clks on all other QC SoCs and
sc8280xp seems to be the exception here. So I'll continue to use floor
ops for sdcc.

> 
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
>> +    F(400000, P_BI_TCXO, 12, 1, 4),
>> +    F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
>> +    F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
>> +    .cmd_rcgr = 0x16018,
>> +    .mnd_width = 8,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_sdcc4_apps_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_floor_ops,
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
>> +    F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
>> +    F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> +    F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
>> +    F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
>> +    .cmd_rcgr = 0x77030,
>> +    .mnd_width = 8,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_ufs_phy_axi_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
> 
> This looks correct since you want to persist this clock in suspend 
> presumably.
> 
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
>> +    F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
>> +    F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
>> +    F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
>> +    .cmd_rcgr = 0x77080,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_7,
>> +    .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_ufs_phy_ice_core_clk_src",
>> +        .parent_data = gcc_parent_data_7,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_7),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
>> +    .cmd_rcgr = 0x770b4,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_3,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_ufs_phy_phy_aux_clk_src",
>> +        .parent_data = gcc_parent_data_3,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_3),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
> 
> but then why not ufs_phy_ice_core and ufs_phy_phy_aux_clk
> 
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
>> +    F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> +    F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
>> +    F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
>> +    .cmd_rcgr = 0x77098,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_ufs_phy_unipro_core_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
> 
> but back to the parked clock here.
> 
> Shoudln't all of the UFS related clocks park in suspend ?
> 
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
>> +    F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
>> +    F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_usb20_master_clk_src = {
>> +    .cmd_rcgr = 0x2902c,
>> +    .mnd_width = 8,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_usb20_master_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_usb20_master_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
>> +    .cmd_rcgr = 0x29158,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_usb20_mock_utmi_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
>> +    F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
>> +    F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
>> +    F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
>> +    F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
>> +    .cmd_rcgr = 0x1702c,
>> +    .mnd_width = 8,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_usb30_mp_master_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_shared_ops,
>> +    },
>> +};
>> +
>> +static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
>> +    .cmd_rcgr = 0x17158,
>> +    .mnd_width = 0,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_parent_map_0,
>> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_usb30_mp_mock_utmi_clk_src",
>> +        .parent_data = gcc_parent_data_0,
>> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> +        .flags = CLK_SET_RATE_PARENT,
>> +        .ops = &clk_rcg2_ops,
> 
> This is another discontinuinty with sc8280xp.
> 
> Could you have a look through the sc8280xp gcc and do an aduit for 
> clk_rcg2_shared_ops as against sc8380xp ?

ack, will do a quick audit before the re-spin.

> 
> ---
> bod
Johan Hovold Nov. 17, 2023, 8:13 a.m. UTC | #5 
On Fri, Nov 17, 2023 at 09:26:18AM +0530, Sibi Sankar wrote:
> On 10/25/23 22:10, Bryan O'Donoghue wrote:
> > On 25/10/2023 14:33, Sibi Sankar wrote:

> >> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
> >> +    .cmd_rcgr = 0x14018,
> >> +    .mnd_width = 8,
> >> +    .hid_width = 5,
> >> +    .parent_map = gcc_parent_map_9,
> >> +    .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
> >> +    .clkr.hw.init = &(const struct clk_init_data) {
> >> +        .name = "gcc_sdcc2_apps_clk_src",
> >> +        .parent_data = gcc_parent_data_9,
> >> +        .num_parents = ARRAY_SIZE(gcc_parent_data_9),
> >> +        .flags = CLK_SET_RATE_PARENT,
> >> +        .ops = &clk_rcg2_floor_ops,
> > 
> > diff sc8280xp..sc8380xp
> > 
> > Here you've used floor instead of shared ops, why is that ?
> 
> We seem to use floor ops for sdcc clks on all other QC SoCs and
> sc8280xp seems to be the exception here. So I'll continue to use floor
> ops for sdcc.

> >> +static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
> >> +    .cmd_rcgr = 0x17158,
> >> +    .mnd_width = 0,
> >> +    .hid_width = 5,
> >> +    .parent_map = gcc_parent_map_0,
> >> +    .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> >> +    .clkr.hw.init = &(const struct clk_init_data) {
> >> +        .name = "gcc_usb30_mp_mock_utmi_clk_src",
> >> +        .parent_data = gcc_parent_data_0,
> >> +        .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> >> +        .flags = CLK_SET_RATE_PARENT,
> >> +        .ops = &clk_rcg2_ops,
> > 
> > This is another discontinuinty with sc8280xp.
> > 
> > Could you have a look through the sc8280xp gcc and do an aduit for 
> > clk_rcg2_shared_ops as against sc8380xp ?
> 
> ack, will do a quick audit before the re-spin.

Please trim unnecessary context from your replies. You quoted some 1400
lines of irrelevant clock structs when all you needed was something like
the above.

Not trimming replies makes it a pain to read your mails and to revisit
threads like this one, for example, in the lore web archives.

Johan
Bryan O'Donoghue Nov. 17, 2023, 2:24 p.m. UTC | #6 
On 17/11/2023 03:56, Sibi Sankar wrote:
>>
>> This is another discontinuinty with sc8280xp.
>>
>> Could you have a look through the sc8280xp gcc and do an aduit for 
>> clk_rcg2_shared_ops as against sc8380xp ?
> 
> ack, will do a quick audit before the re-spin.

A best guess will do, we will "shake out the bugs" through 
suspend/resume real use cases anyway but, worth a quick pass since you 
are doing a v2 for the SoC name.

---
bod