| Message ID | 20231115032515.4249-3-quic_luoj@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | add MDIO changes on ipq5332 platform | expand |
On 15.11.2023 04:25, Luo Jie wrote: > For the platform ipq5332, the related GCC clocks need to be enabled > to make the GPIO reset of the MDIO slave devices taking effect. > > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> [...] > static int ipq4019_mdio_wait_busy(struct mii_bus *bus) > @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus) > u32 val; > int ret; > > + /* For the platform ipq5332, there are two uniphy available to connect the > + * ethernet devices, the uniphy gcc clock should be enabled for resetting > + * the connected device such as qca8386 switch or qca8081 PHY effectively. > + */ > + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) { Would that not also be taken care of in the phy driver? Konrad
On 11/20/2023 10:22 PM, Konrad Dybcio wrote: > On 15.11.2023 04:25, Luo Jie wrote: >> For the platform ipq5332, the related GCC clocks need to be enabled >> to make the GPIO reset of the MDIO slave devices taking effect. >> >> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > [...] > >> static int ipq4019_mdio_wait_busy(struct mii_bus *bus) >> @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus) >> u32 val; >> int ret; >> >> + /* For the platform ipq5332, there are two uniphy available to connect the >> + * ethernet devices, the uniphy gcc clock should be enabled for resetting >> + * the connected device such as qca8386 switch or qca8081 PHY effectively. >> + */ >> + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) { > Would that not also be taken care of in the phy driver? > > Konrad Hi Konrad, These clocks are the SOC clocks that is not related to the PHY type. no matter what kind of PHY is connected, we also need to configure these clocks.
On Tue, Nov 21, 2023 at 06:28:54PM +0800, Jie Luo wrote: > > > On 11/20/2023 10:22 PM, Konrad Dybcio wrote: > > On 15.11.2023 04:25, Luo Jie wrote: > > > For the platform ipq5332, the related GCC clocks need to be enabled > > > to make the GPIO reset of the MDIO slave devices taking effect. > > > > > > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > > [...] > > > > > static int ipq4019_mdio_wait_busy(struct mii_bus *bus) > > > @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus) > > > u32 val; > > > int ret; > > > + /* For the platform ipq5332, there are two uniphy available to connect the > > > + * ethernet devices, the uniphy gcc clock should be enabled for resetting > > > + * the connected device such as qca8386 switch or qca8081 PHY effectively. > > > + */ > > > + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) { > > Would that not also be taken care of in the phy driver? > > > > Konrad > > Hi Konrad, > These clocks are the SOC clocks that is not related to the PHY type. > no matter what kind of PHY is connected, we also need to configure > these clocks. Hi Jie You can avoid lots of these questions by making your commit message better. Assume the reader does not know the clock tree for this device. With a bit of experience, you can guess what reviewers are going to ask, and answer those questions in the commit message. Andrew
On 11/21/2023 10:04 PM, Andrew Lunn wrote: > On Tue, Nov 21, 2023 at 06:28:54PM +0800, Jie Luo wrote: >> >> >> On 11/20/2023 10:22 PM, Konrad Dybcio wrote: >>> On 15.11.2023 04:25, Luo Jie wrote: >>>> For the platform ipq5332, the related GCC clocks need to be enabled >>>> to make the GPIO reset of the MDIO slave devices taking effect. >>>> >>>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> >>> [...] >>> >>>> static int ipq4019_mdio_wait_busy(struct mii_bus *bus) >>>> @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus) >>>> u32 val; >>>> int ret; >>>> + /* For the platform ipq5332, there are two uniphy available to connect the >>>> + * ethernet devices, the uniphy gcc clock should be enabled for resetting >>>> + * the connected device such as qca8386 switch or qca8081 PHY effectively. >>>> + */ >>>> + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) { >>> Would that not also be taken care of in the phy driver? >>> >>> Konrad >> >> Hi Konrad, >> These clocks are the SOC clocks that is not related to the PHY type. >> no matter what kind of PHY is connected, we also need to configure >> these clocks. > > Hi Jie > > You can avoid lots of these questions by making your commit message > better. Assume the reader does not know the clock tree for this > device. With a bit of experience, you can guess what reviewers are > going to ask, and answer those questions in the commit message. > > Andrew Hi Andrew, Got it, will take more attention on the commit message to make the code clearly in future patches, thanks for the suggestion.
On Wed, Nov 15, 2023 at 11:25:08AM +0800, Luo Jie wrote: > For the platform ipq5332, the related GCC clocks need to be enabled > to make the GPIO reset of the MDIO slave devices taking effect. > > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > --- > drivers/net/mdio/mdio-ipq4019.c | 67 +++++++++++++++++++++++++++++---- > 1 file changed, 60 insertions(+), 7 deletions(-) > > diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c > index 9d444f5f7efb..a77982a1a1e1 100644 > --- a/drivers/net/mdio/mdio-ipq4019.c > +++ b/drivers/net/mdio/mdio-ipq4019.c ... > +const char *const mdio_clk_name[] = { > + "gcc_mdio_ahb_clk", > + "gcc_uniphy0_ahb_clk", > + "gcc_uniphy0_sys_clk", > + "gcc_uniphy1_ahb_clk", > + "gcc_uniphy1_sys_clk" > }; Hi Luo Jie, A minor nit from my side: It appears that mdio_clk_name is only used in this file. If so it should be declared as static. ...
On 11/27/2023 5:37 PM, Simon Horman wrote: > On Wed, Nov 15, 2023 at 11:25:08AM +0800, Luo Jie wrote: >> For the platform ipq5332, the related GCC clocks need to be enabled >> to make the GPIO reset of the MDIO slave devices taking effect. >> >> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> >> --- >> drivers/net/mdio/mdio-ipq4019.c | 67 +++++++++++++++++++++++++++++---- >> 1 file changed, 60 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c >> index 9d444f5f7efb..a77982a1a1e1 100644 >> --- a/drivers/net/mdio/mdio-ipq4019.c >> +++ b/drivers/net/mdio/mdio-ipq4019.c > > ... > >> +const char *const mdio_clk_name[] = { >> + "gcc_mdio_ahb_clk", >> + "gcc_uniphy0_ahb_clk", >> + "gcc_uniphy0_sys_clk", >> + "gcc_uniphy1_ahb_clk", >> + "gcc_uniphy1_sys_clk" >> }; > > Hi Luo Jie, > > A minor nit from my side: It appears that mdio_clk_name is only > used in this file. If so it should be declared as static. > > ... Hi Simon, The mdio_clk_name is only used in this file, will update to use static, thanks.
diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 9d444f5f7efb..a77982a1a1e1 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -34,16 +34,35 @@ /* MDIO clock source frequency is fixed to 100M */ #define IPQ_MDIO_CLK_RATE 100000000 +#define IPQ_UNIPHY_AHB_CLK_RATE 100000000 +#define IPQ_UNIPHY_SYS_CLK_RATE 24000000 #define IPQ_PHY_SET_DELAY_US 100000 /* Maximum SOC PCS(uniphy) number on IPQ platform */ #define ETH_LDO_RDY_CNT 3 +enum mdio_clk_id { + MDIO_CLK_MDIO_AHB, + MDIO_CLK_UNIPHY0_AHB, + MDIO_CLK_UNIPHY0_SYS, + MDIO_CLK_UNIPHY1_AHB, + MDIO_CLK_UNIPHY1_SYS, + MDIO_CLK_CNT +}; + struct ipq4019_mdio_data { void __iomem *membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; - struct clk *mdio_clk; + struct clk *clk[MDIO_CLK_CNT]; +}; + +const char *const mdio_clk_name[] = { + "gcc_mdio_ahb_clk", + "gcc_uniphy0_ahb_clk", + "gcc_uniphy0_sys_clk", + "gcc_uniphy1_ahb_clk", + "gcc_uniphy1_sys_clk" }; static int ipq4019_mdio_wait_busy(struct mii_bus *bus) @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus) u32 val; int ret; + /* For the platform ipq5332, there are two uniphy available to connect the + * ethernet devices, the uniphy gcc clock should be enabled for resetting + * the connected device such as qca8386 switch or qca8081 PHY effectively. + */ + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) { + int i; + unsigned long rate = 0; + + for (i = MDIO_CLK_UNIPHY0_AHB; i < MDIO_CLK_CNT; i++) { + switch (i) { + case MDIO_CLK_UNIPHY0_AHB: + case MDIO_CLK_UNIPHY1_AHB: + rate = IPQ_UNIPHY_AHB_CLK_RATE; + break; + case MDIO_CLK_UNIPHY0_SYS: + case MDIO_CLK_UNIPHY1_SYS: + rate = IPQ_UNIPHY_SYS_CLK_RATE; + break; + default: + break; + } + + ret = clk_set_rate(priv->clk[i], rate); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[i]); + if (ret) + return ret; + } + } + /* To indicate CMN_PLL that ethernet_ldo has been ready if platform resource 1 * or more resource are specified in the device tree. */ @@ -225,11 +276,11 @@ static int ipq_mdio_reset(struct mii_bus *bus) } /* Configure MDIO clock source frequency if clock is specified in the device tree */ - ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE); + ret = clk_set_rate(priv->clk[MDIO_CLK_MDIO_AHB], IPQ_MDIO_CLK_RATE); if (ret) return ret; - ret = clk_prepare_enable(priv->mdio_clk); + ret = clk_prepare_enable(priv->clk[MDIO_CLK_MDIO_AHB]); if (ret == 0) mdelay(10); @@ -253,10 +304,6 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) if (IS_ERR(priv->membase)) return PTR_ERR(priv->membase); - priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "gcc_mdio_ahb_clk"); - if (IS_ERR(priv->mdio_clk)) - return PTR_ERR(priv->mdio_clk); - /* The platform resource is provided on the chipset IPQ5018/IPQ5332 */ /* This resource is optional */ for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) { @@ -266,6 +313,12 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) res->start, resource_size(res)); } + for (ret = 0; ret < MDIO_CLK_CNT; ret++) { + priv->clk[ret] = devm_clk_get_optional(&pdev->dev, mdio_clk_name[ret]); + if (IS_ERR(priv->clk[ret])) + return PTR_ERR(priv->clk[ret]); + } + bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; bus->write = ipq4019_mdio_write_c22;
For the platform ipq5332, the related GCC clocks need to be enabled to make the GPIO reset of the MDIO slave devices taking effect. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- drivers/net/mdio/mdio-ipq4019.c | 67 +++++++++++++++++++++++++++++---- 1 file changed, 60 insertions(+), 7 deletions(-)