| Message ID | 20231117032500.2923624-1-yangcong5@huaqin.corp-partner.google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V2] drm/panel: boe-tv101wum-nl6: Fine tune Himax83102-j02 panel HFP and HBP | expand |
Hi, On Thu, Nov 16, 2023 at 7:25 PM Cong Yang <yangcong5@huaqin.corp-partner.google.com> wrote: > > The refresh reported by modetest is 60.46Hz, and the actual measurement > is 60.01Hz, which is outside the expected tolerance. Presumably you've swapped the numbers above? The value reported by modetest is 60.01Hz and the actual measurement is 60.46Hz? > Adjust hporch and > pixel clock to fix it. After repair, modetest and actual measurement were > all 60.01Hz. > > Modetest refresh = Pixel CLK/ htotal* vtotal, but measurement frame rate > is HS->LP cycle time(Vblanking). Measured frame rate is not only affected > by Htotal/Vtotal/pixel clock, also affecte by Lane-num/PixelBit/LineTime s/affecte/affected For me, the important part would be to explain the reason for the difference. I assume that the DSI controller could not make the mode that we requested exactly (presumably it's PLL couldn't generate the exact pixel clock?). This new mode was picked to be achievable by the DSI controller on the system that the panel is used on. > /DSI CLK. If you use a different SOC platform mipi controller, you may > need to readjust these parameters. Now this panel looks like it's only used > by me on the MTK platform, so let's change this set of parameters. > > Fixes: 1bc2ef065f13 ("drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel") > Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> > --- > Chage since V1: > > - Update commit message. > > V1: https://lore.kernel.org/all/20231110094553.2361842-1-yangcong5@huaqin.corp-partner.google.com > --- > drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) As per discussion in V1, I'm OK with this. Reviewed-by: Douglas Anderson <dianders@chromium.org> I'll probably give it at least another week before applying in case anyone else wants to speak up. It would be nice if you could send a V3 with a few more touchups to the commit message, especially since the 60.01 and 60.46 numbers were backward (unless I'm mistaken). -Doug
Hi, On Sat, Nov 18, 2023 at 1:11 AM Doug Anderson <dianders@chromium.org> wrote: > > Hi, > > On Thu, Nov 16, 2023 at 7:25 PM Cong Yang > <yangcong5@huaqin.corp-partner.google.com> wrote: > > > > The refresh reported by modetest is 60.46Hz, and the actual measurement > > is 60.01Hz, which is outside the expected tolerance. > > Presumably you've swapped the numbers above? The value reported by > modetest is 60.01Hz and the actual measurement is 60.46Hz? No, the value reported by modetest is 60.46Hz. > > > Adjust hporch and > > pixel clock to fix it. After repair, modetest and actual measurement were > > all 60.01Hz. > > > > Modetest refresh = Pixel CLK/ htotal* vtotal, but measurement frame rate > > is HS->LP cycle time(Vblanking). Measured frame rate is not only affected > > by Htotal/Vtotal/pixel clock, also affecte by Lane-num/PixelBit/LineTime > > s/affecte/affected > > For me, the important part would be to explain the reason for the > difference. I assume that the DSI controller could not make the mode > that we requested exactly (presumably it's PLL couldn't generate the > exact pixel clock?). This new mode was picked to be achievable by the > DSI controller on the system that the panel is used on. > > > > /DSI CLK. If you use a different SOC platform mipi controller, you may > > need to readjust these parameters. Now this panel looks like it's only used > > by me on the MTK platform, so let's change this set of parameters. > > > > Fixes: 1bc2ef065f13 ("drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel") > > Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> > > --- > > Chage since V1: > > > > - Update commit message. > > > > V1: https://lore.kernel.org/all/20231110094553.2361842-1-yangcong5@huaqin.corp-partner.google.com > > --- > > drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > As per discussion in V1, I'm OK with this. > > Reviewed-by: Douglas Anderson <dianders@chromium.org> > > I'll probably give it at least another week before applying in case > anyone else wants to speak up. It would be nice if you could send a V3 > with a few more touchups to the commit message, especially since the > 60.01 and 60.46 numbers were backward (unless I'm mistaken). > > > -Doug
Hi, On Sun, Nov 19, 2023 at 5:33 PM cong yang <yangcong5@huaqin.corp-partner.google.com> wrote: > > Hi, > > On Sat, Nov 18, 2023 at 1:11 AM Doug Anderson <dianders@chromium.org> wrote: > > > > Hi, > > > > On Thu, Nov 16, 2023 at 7:25 PM Cong Yang > > <yangcong5@huaqin.corp-partner.google.com> wrote: > > > > > > The refresh reported by modetest is 60.46Hz, and the actual measurement > > > is 60.01Hz, which is outside the expected tolerance. > > > > Presumably you've swapped the numbers above? The value reported by > > modetest is 60.01Hz and the actual measurement is 60.46Hz? > > No, the value reported by modetest is 60.46Hz. Indeed. I somehow assumed that the old value of "clock / (htotal * vtotal)" would have been the one that was closer to 60 Hz, but doing the math I agree with you. Specifically: >>> 161600000 / ((1200 + 40 + 20 + 40) * (1920 + 116 + 8 + 12)) 60.46093983837174 >>> 162850000 / ((1200 + 50 + 20 + 50) * (1920 + 116 + 8 + 12)) 60.005453366348306 Thanks for correcting me! -Doug
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c index 4f370bc6dca8..5f7e7dee8a82 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -1768,11 +1768,11 @@ static const struct panel_desc starry_qfh032011_53g_desc = { }; static const struct drm_display_mode starry_himax83102_j02_default_mode = { - .clock = 161600, + .clock = 162850, .hdisplay = 1200, - .hsync_start = 1200 + 40, - .hsync_end = 1200 + 40 + 20, - .htotal = 1200 + 40 + 20 + 40, + .hsync_start = 1200 + 50, + .hsync_end = 1200 + 50 + 20, + .htotal = 1200 + 50 + 20 + 50, .vdisplay = 1920, .vsync_start = 1920 + 116, .vsync_end = 1920 + 116 + 8,
The refresh reported by modetest is 60.46Hz, and the actual measurement is 60.01Hz, which is outside the expected tolerance. Adjust hporch and pixel clock to fix it. After repair, modetest and actual measurement were all 60.01Hz. Modetest refresh = Pixel CLK/ htotal* vtotal, but measurement frame rate is HS->LP cycle time(Vblanking). Measured frame rate is not only affected by Htotal/Vtotal/pixel clock, also affecte by Lane-num/PixelBit/LineTime /DSI CLK. If you use a different SOC platform mipi controller, you may need to readjust these parameters. Now this panel looks like it's only used by me on the MTK platform, so let's change this set of parameters. Fixes: 1bc2ef065f13 ("drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel") Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> --- Chage since V1: - Update commit message. V1: https://lore.kernel.org/all/20231110094553.2361842-1-yangcong5@huaqin.corp-partner.google.com --- drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)