diff mbox series

[v2] target/riscv: don't verify ISA compatibility for zicntr and zihpm

Message ID 20231114123913.536194-1-chigot@adacore.com (mailing list archive)
State New, archived
Headers show
Series [v2] target/riscv: don't verify ISA compatibility for zicntr and zihpm | expand

Commit Message

Clément Chigot Nov. 14, 2023, 12:39 p.m. UTC 
The extensions zicntr and zihpm were officially added in the privilege
instruction set specification 1.12. However, QEMU has been implemented
them long before it and thus they are forced to be on during the cpu
initialization to ensure compatibility (see riscv_cpu_init).
riscv_cpu_disable_priv_spec_isa_exts was not updated when the above
behavior was introduced, resulting in these extensions to be disabled
after all.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Fixes: c004099330 ("target/riscv: add zicntr extension flag for TCG")
Fixes: 0824121660 ("target/riscv: add zihpm extension flag for TCG")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/tcg/tcg-cpu.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Alistair Francis Nov. 21, 2023, 3:43 a.m. UTC | #1 
On Wed, Nov 15, 2023 at 12:46 AM Clément Chigot <chigot@adacore.com> wrote:
>
> The extensions zicntr and zihpm were officially added in the privilege
> instruction set specification 1.12. However, QEMU has been implemented
> them long before it and thus they are forced to be on during the cpu
> initialization to ensure compatibility (see riscv_cpu_init).
> riscv_cpu_disable_priv_spec_isa_exts was not updated when the above
> behavior was introduced, resulting in these extensions to be disabled
> after all.
>
> Signed-off-by: Clément Chigot <chigot@adacore.com>
> Fixes: c004099330 ("target/riscv: add zicntr extension flag for TCG")
> Fixes: 0824121660 ("target/riscv: add zihpm extension flag for TCG")
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/tcg/tcg-cpu.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 08adad304d..8a35683a34 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -250,6 +250,15 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
>      for (edata = isa_edata_arr; edata && edata->name; edata++) {
>          if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
>              (env->priv_ver < edata->min_version)) {
> +            /*
> +             * These two extensions are always enabled as they were supported
> +             * by QEMU before they were added as extensions in the ISA.
> +             */
> +            if (!strcmp(edata->name, "zicntr") ||
> +                !strcmp(edata->name, "zihpm")) {
> +                continue;
> +            }
> +
>              isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
>  #ifndef CONFIG_USER_ONLY
>              warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> --
> 2.25.1
>
>
Alistair Francis Nov. 21, 2023, 3:48 a.m. UTC | #2 
On Wed, Nov 15, 2023 at 12:46 AM Clément Chigot <chigot@adacore.com> wrote:
>
> The extensions zicntr and zihpm were officially added in the privilege
> instruction set specification 1.12. However, QEMU has been implemented
> them long before it and thus they are forced to be on during the cpu
> initialization to ensure compatibility (see riscv_cpu_init).
> riscv_cpu_disable_priv_spec_isa_exts was not updated when the above
> behavior was introduced, resulting in these extensions to be disabled
> after all.
>
> Signed-off-by: Clément Chigot <chigot@adacore.com>
> Fixes: c004099330 ("target/riscv: add zicntr extension flag for TCG")
> Fixes: 0824121660 ("target/riscv: add zihpm extension flag for TCG")
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/tcg/tcg-cpu.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 08adad304d..8a35683a34 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -250,6 +250,15 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
>      for (edata = isa_edata_arr; edata && edata->name; edata++) {
>          if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
>              (env->priv_ver < edata->min_version)) {
> +            /*
> +             * These two extensions are always enabled as they were supported
> +             * by QEMU before they were added as extensions in the ISA.
> +             */
> +            if (!strcmp(edata->name, "zicntr") ||
> +                !strcmp(edata->name, "zihpm")) {
> +                continue;
> +            }
> +
>              isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
>  #ifndef CONFIG_USER_ONLY
>              warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 08adad304d..8a35683a34 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -250,6 +250,15 @@  static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
     for (edata = isa_edata_arr; edata && edata->name; edata++) {
         if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
             (env->priv_ver < edata->min_version)) {
+            /*
+             * These two extensions are always enabled as they were supported
+             * by QEMU before they were added as extensions in the ISA.
+             */
+            if (!strcmp(edata->name, "zicntr") ||
+                !strcmp(edata->name, "zihpm")) {
+                continue;
+            }
+
             isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
 #ifndef CONFIG_USER_ONLY
             warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx