| Message ID | 2736e884-4b28-4ee9-b23e-24e763355d1f@suse.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] x86/cpuid: enumerate and expose PREFETCHIT{0,1} | expand |
On 22/11/2023 7:43 am, Jan Beulich wrote: > --- a/xen/tools/gen-cpuid.py > +++ b/xen/tools/gen-cpuid.py > @@ -274,7 +274,7 @@ def crunch_numbers(state): > # superpages, PCID and PKU are only available in 4 level paging. > # NO_LMSL indicates the absense of Long Mode Segment Limits, which > # have been dropped in hardware. > - LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL], > + LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, PREFETCHI], I know this is what the ISE says, but I'm not sure it's a legitimate dependency. It is an implementation detail that Intel depend on a RIP-relative address, but there are no architectural reason why other implementations couldn't make this work in 32bit too. The worst that happens without this dependency is that 32bit-only VMs see a hint bit about certain NOPs having uarch side effects, which they'll ignore for other reasons. So I recommend dropping the dependency. If you're happy, then Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> ~Andrew
On 22.11.2023 13:25, Andrew Cooper wrote: > On 22/11/2023 7:43 am, Jan Beulich wrote: >> --- a/xen/tools/gen-cpuid.py >> +++ b/xen/tools/gen-cpuid.py >> @@ -274,7 +274,7 @@ def crunch_numbers(state): >> # superpages, PCID and PKU are only available in 4 level paging. >> # NO_LMSL indicates the absense of Long Mode Segment Limits, which >> # have been dropped in hardware. >> - LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL], >> + LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, PREFETCHI], > > I know this is what the ISE says, but I'm not sure it's a legitimate > dependency. > > It is an implementation detail that Intel depend on a RIP-relative > address, but there are no architectural reason why other implementations > couldn't make this work in 32bit too. > > The worst that happens without this dependency is that 32bit-only VMs > see a hint bit about certain NOPs having uarch side effects, which > they'll ignore for other reasons. I'm okay either way. Adding the dependency was the only reason to have a v2 ... > So I recommend dropping the dependency. If you're happy, then > Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Thanks. Jan
--- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -220,6 +220,8 @@ static const char *const str_7d1[32] = { [ 4] = "avx-vnni-int8", [ 5] = "avx-ne-convert", + [14] = "prefetchi", + [18] = "cet-sss", }; --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -310,6 +310,7 @@ XEN_CPUFEATURE(AVX_VNNI_INT8, 15*32 /* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */ XEN_CPUFEATURE(AVX_VNNI_INT8, 15*32+ 4) /*A AVX-VNNI-INT8 Instructions */ XEN_CPUFEATURE(AVX_NE_CONVERT, 15*32+ 5) /*A AVX-NE-CONVERT Instructions */ +XEN_CPUFEATURE(PREFETCHI, 15*32+14) /*A PREFETCHIT{0,1} Instructions */ XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow Stacks safe to use */ /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -274,7 +274,7 @@ def crunch_numbers(state): # superpages, PCID and PKU are only available in 4 level paging. # NO_LMSL indicates the absense of Long Mode Segment Limits, which # have been dropped in hardware. - LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL], + LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, PREFETCHI], # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors.
There's nothing else that should need doing in order for guests to be able to use these insns, as the encodings are in what's otherwise NOP space. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- v2: gen-cpuid adjustment.