diff mbox series

xen/arm: gicv3: clean up GICD_CTRL write

Message ID 20231122144602.2282417-1-stewart.hildebrand@amd.com (mailing list archive)
State New, archived
Headers show
Series xen/arm: gicv3: clean up GICD_CTRL write | expand

Commit Message

Stewart Hildebrand Nov. 22, 2023, 2:46 p.m. UTC 
GICD_CTL_ENABLE is a GICv2 bit. Remove it. The definitions of
GICD_CTL_ENABLE and GICD_CTLR_ENABLE_G1 are identical, so the value
written is unchanged.

Signed-off-by: Stewart Hildebrand <stewart.hildebrand@amd.com>
---
 xen/arch/arm/gic-v3.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


base-commit: c22fe7213c9b1f99cbc64c33e391afa223f9cd08

Comments

Julien Grall Nov. 23, 2023, 10:52 a.m. UTC | #1 
Hi Stewart,

On 22/11/2023 14:46, Stewart Hildebrand wrote:
> GICD_CTL_ENABLE is a GICv2 bit. Remove it. The definitions of
> GICD_CTL_ENABLE and GICD_CTLR_ENABLE_G1 are identical, so the value
> written is unchanged.

Thanks for spotting it. Maybe we should move GICv2 specific definitions 
out of gic.h. Anyway, this is a separate clean-up. So...

> 
> Signed-off-by: Stewart Hildebrand <stewart.hildebrand@amd.com>

...

Reviewed-by: Julien Grall <jgrall@amazon.com>

Cheers,
Julien Grall Nov. 23, 2023, 10:54 a.m. UTC | #2 
On 23/11/2023 10:52, Julien Grall wrote:
> Hi Stewart,
> 
> On 22/11/2023 14:46, Stewart Hildebrand wrote:
>> GICD_CTL_ENABLE is a GICv2 bit. Remove it. The definitions of
>> GICD_CTL_ENABLE and GICD_CTLR_ENABLE_G1 are identical, so the value
>> written is unchanged.
> 
> Thanks for spotting it. Maybe we should move GICv2 specific definitions 
> out of gic.h. Anyway, this is a separate clean-up. So...
> 
>>
>> Signed-off-by: Stewart Hildebrand <stewart.hildebrand@amd.com>
> 
> ...
> 
> Reviewed-by: Julien Grall <jgrall@amazon.com>

And committed.

Cheers,
diff mbox series

Patch

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 172ff8c005ff..9b35a8c8a735 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -633,8 +633,8 @@  static void __init gicv3_dist_init(void)
     gicv3_dist_wait_for_rwp();
 
     /* Turn on the distributor */
-    writel_relaxed(GICD_CTL_ENABLE | GICD_CTLR_ARE_NS |
-                GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, GICD + GICD_CTLR);
+    writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A |
+                   GICD_CTLR_ENABLE_G1, GICD + GICD_CTLR);
 
     /* Route all global IRQs to this CPU */
     affinity = gicv3_mpidr_to_affinity(smp_processor_id());