| Message ID | 20231122121235.827122-5-peterlin@andestech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Support Andes PMU extension | expand |
On Wed, Nov 22, 2023 at 08:12:26PM +0800, Yu Chien Peter Lin wrote: > Add "andestech,cpu-intc" compatible string to indicate that > Andes specific local interrupt is supported on the core, > e.g. AX45MP cores have 3 types of non-standard local interrupt > can be handled in supervisor mode: > > - Slave port ECC error interrupt > - Bus write transaction error interrupt > - Performance monitor overflow interrupt > > These interrupts are enabled/disabled via a custom register > SLIE instead of the standard interrupt enable register SIE. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor. > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Updated commit message > - Fixed possible compatibles for Andes INTC > Changes v3 -> v4: > - Add const entry instead of enum (Suggested by Conor) > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index f392e367d673..50307554478f 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -100,7 +100,11 @@ properties: > const: 1 > > compatible: > - const: riscv,cpu-intc > + oneOf: > + - items: > + - const: andestech,cpu-intc > + - const: riscv,cpu-intc > + - const: riscv,cpu-intc > > interrupt-controller: true > > -- > 2.34.1 >
On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > > Add "andestech,cpu-intc" compatible string to indicate that > Andes specific local interrupt is supported on the core, > e.g. AX45MP cores have 3 types of non-standard local interrupt > can be handled in supervisor mode: > > - Slave port ECC error interrupt > - Bus write transaction error interrupt > - Performance monitor overflow interrupt > > These interrupts are enabled/disabled via a custom register > SLIE instead of the standard interrupt enable register SIE. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Updated commit message > - Fixed possible compatibles for Andes INTC > Changes v3 -> v4: > - Add const entry instead of enum (Suggested by Conor) > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index f392e367d673..50307554478f 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -100,7 +100,11 @@ properties: > const: 1 > > compatible: > - const: riscv,cpu-intc > + oneOf: > + - items: > + - const: andestech,cpu-intc given that the first patch renames andestech -> andes, do you want to follow the same here? > + - const: riscv,cpu-intc > + - const: riscv,cpu-intc > > interrupt-controller: true > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Cheers, Prabhakar > -- > 2.34.1 > >
On Fri, Nov 24, 2023 at 03:03:51PM +0000, Lad, Prabhakar wrote: > On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin > <peterlin@andestech.com> wrote: > > > > Add "andestech,cpu-intc" compatible string to indicate that > > Andes specific local interrupt is supported on the core, > > e.g. AX45MP cores have 3 types of non-standard local interrupt > > can be handled in supervisor mode: > > > > - Slave port ECC error interrupt > > - Bus write transaction error interrupt > > - Performance monitor overflow interrupt > > > > These interrupts are enabled/disabled via a custom register > > SLIE instead of the standard interrupt enable register SIE. > > > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > > --- > > Changes v1 -> v2: > > - New patch > > Changes v2 -> v3: > > - Updated commit message > > - Fixed possible compatibles for Andes INTC > > Changes v3 -> v4: > > - Add const entry instead of enum (Suggested by Conor) > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index f392e367d673..50307554478f 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -100,7 +100,11 @@ properties: > > const: 1 > > > > compatible: > > - const: riscv,cpu-intc > > + oneOf: > > + - items: > > + - const: andestech,cpu-intc > given that the first patch renames andestech -> andes, do you want to > follow the same here? No, that's their vendor prefix, they're stuck with it.
Hi Prabhakar, On Fri, Nov 24, 2023 at 03:03:51PM +0000, Lad, Prabhakar wrote: > On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin > <peterlin@andestech.com> wrote: > > > > Add "andestech,cpu-intc" compatible string to indicate that > > Andes specific local interrupt is supported on the core, > > e.g. AX45MP cores have 3 types of non-standard local interrupt > > can be handled in supervisor mode: > > > > - Slave port ECC error interrupt > > - Bus write transaction error interrupt > > - Performance monitor overflow interrupt > > > > These interrupts are enabled/disabled via a custom register > > SLIE instead of the standard interrupt enable register SIE. > > > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > > --- > > Changes v1 -> v2: > > - New patch > > Changes v2 -> v3: > > - Updated commit message > > - Fixed possible compatibles for Andes INTC > > Changes v3 -> v4: > > - Add const entry instead of enum (Suggested by Conor) > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index f392e367d673..50307554478f 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -100,7 +100,11 @@ properties: > > const: 1 > > > > compatible: > > - const: riscv,cpu-intc > > + oneOf: > > + - items: > > + - const: andestech,cpu-intc > given that the first patch renames andestech -> andes, do you want to > follow the same here? Thanks for pointing this out. We would like to use "andestech" for compatible string. Documentation/devicetree/bindings/vendor-prefixes.yaml 118: "^andestech,.*": 119- description: Andes Technology Corporation > > + - const: riscv,cpu-intc > > + - const: riscv,cpu-intc > > > > interrupt-controller: true > > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for the review! Best regards, Peter Lin > Cheers, > Prabhakar > > > -- > > 2.34.1 > > > >
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index f392e367d673..50307554478f 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -100,7 +100,11 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + oneOf: + - items: + - const: andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc interrupt-controller: true
Add "andestech,cpu-intc" compatible string to indicate that Andes specific local interrupt is supported on the core, e.g. AX45MP cores have 3 types of non-standard local interrupt can be handled in supervisor mode: - Slave port ECC error interrupt - Bus write transaction error interrupt - Performance monitor overflow interrupt These interrupts are enabled/disabled via a custom register SLIE instead of the standard interrupt enable register SIE. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Updated commit message - Fixed possible compatibles for Andes INTC Changes v3 -> v4: - Add const entry instead of enum (Suggested by Conor) --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)