Message ID | 20231122125454.3454671-1-andyshrk@163.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add VOP2 support on rk3588 | expand |
On Wed, Nov 22, 2023 at 08:54:54PM +0800, Andy Yan wrote: > From: Andy Yan <andy.yan@rock-chips.com> > > The vop2 need to reference more grf(system grf, vop grf, vo0/1 grf,etc) > in the upcoming rk3588. > > So we rename the current system grf to sys_grf. > > Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha > --- > > (no changes since v1) > > drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > index b32a291c5caa..4bcc405bcf11 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > @@ -190,7 +190,7 @@ struct vop2 { > void __iomem *regs; > struct regmap *map; > > - struct regmap *grf; > + struct regmap *sys_grf; > > /* physical map length of vop2 register */ > u32 len; > @@ -1503,9 +1503,9 @@ static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, > dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; > dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); > if (polflags & POLFLAG_DCLK_INV) > - regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); > + regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); > else > - regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); > + regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); > break; > case ROCKCHIP_VOP2_EP_HDMI0: > die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX; > @@ -2764,7 +2764,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) > return PTR_ERR(vop2->lut_regs); > } > > - vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); > + vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); > > vop2->hclk = devm_clk_get(vop2->dev, "hclk"); > if (IS_ERR(vop2->hclk)) { > -- > 2.34.1 > > >
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index b32a291c5caa..4bcc405bcf11 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -190,7 +190,7 @@ struct vop2 { void __iomem *regs; struct regmap *map; - struct regmap *grf; + struct regmap *sys_grf; /* physical map length of vop2 register */ u32 len; @@ -1503,9 +1503,9 @@ static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); if (polflags & POLFLAG_DCLK_INV) - regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); + regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); else - regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); + regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); break; case ROCKCHIP_VOP2_EP_HDMI0: die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX; @@ -2764,7 +2764,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(vop2->lut_regs); } - vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); + vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); vop2->hclk = devm_clk_get(vop2->dev, "hclk"); if (IS_ERR(vop2->hclk)) {