Message ID | 20231127124735.2080562-1-yung-chuan.liao@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | soundwire: intel_ace2x: fix AC timing setting for ACE2.x | expand |
On Mon, 27 Nov 2023 20:47:35 +0800, Bard Liao wrote: > Start from ACE1.x, DOAISE is added to AC timing control > register bit 5, it combines with DOAIS to get effective > timing, and has the default value 1. > > The current code fills DOAIS, DACTQE and DODS bits to a > variable initialized to zero, and updates the variable > to AC timing control register. With this operation, We > change DOAISE to 0, and force a much more aggressive > timing. The timing is even unable to form a working > waveform on SDA pin. > > [...] Applied, thanks! [1/1] soundwire: intel_ace2x: fix AC timing setting for ACE2.x commit: 393cae5f32d640b9798903702018a48c7a45e59f Best regards,
diff --git a/drivers/soundwire/intel_ace2x.c b/drivers/soundwire/intel_ace2x.c index 82672fcbc2aa..8280baa3254b 100644 --- a/drivers/soundwire/intel_ace2x.c +++ b/drivers/soundwire/intel_ace2x.c @@ -23,8 +23,9 @@ static void intel_shim_vs_init(struct sdw_intel *sdw) { void __iomem *shim_vs = sdw->link_res->shim_vs; - u16 act = 0; + u16 act; + act = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL); u16p_replace_bits(&act, 0x1, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS); act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE; act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DODS;