| Message ID | 20231204182905.2163676-4-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list | expand |
Hi Daniel, kernel test robot noticed the following build warnings: [auto build test WARNING on kvm/queue] [also build test WARNING on mst-vhost/linux-next linus/master v6.7-rc4 next-20231205] [cannot apply to kvm/linux-next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Daniel-Henrique-Barboza/RISC-V-KVM-set-vlenb-in-kvm_riscv_vcpu_alloc_vector_context/20231205-023109 base: https://git.kernel.org/pub/scm/virt/kvm/kvm.git queue patch link: https://lore.kernel.org/r/20231204182905.2163676-4-dbarboza%40ventanamicro.com patch subject: [PATCH 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST config: riscv-defconfig (https://download.01.org/0day-ci/archive/20231205/202312052128.oBSS3Uus-lkp@intel.com/config) compiler: riscv64-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231205/202312052128.oBSS3Uus-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202312052128.oBSS3Uus-lkp@intel.com/ All warnings (new ones prefixed by >>): arch/riscv/kvm/vcpu_onereg.c: In function 'num_vector_regs': >> arch/riscv/kvm/vcpu_onereg.c:991:39: warning: unused variable 'cntx' [-Wunused-variable] 991 | const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; | ^~~~ vim +/cntx +991 arch/riscv/kvm/vcpu_onereg.c 988 989 static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu) 990 { > 991 const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 992 993 if (!riscv_isa_extension_available(vcpu->arch.isa, v)) 994 return 0; 995 996 /* vstart, vl, vtype, vcsr, vlenb; */ 997 return 5; 998 } 999
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index f8c9fa0c03c5..1c91615f47cc 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -986,6 +986,37 @@ static int copy_sbi_ext_reg_indices(u64 __user *uindices) return num_sbi_ext_regs(); } +static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu) +{ + const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + + if (!riscv_isa_extension_available(vcpu->arch.isa, v)) + return 0; + + /* vstart, vl, vtype, vcsr, vlenb; */ + return 5; +} + +static int copy_vector_reg_indices(const struct kvm_vcpu *vcpu, + u64 __user *uindices) +{ + int n = num_vector_regs(vcpu); + u64 reg, size; + + for (int i = 0; i < n; i++) { + size = IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; + reg = KVM_REG_RISCV | size | KVM_REG_RISCV_VECTOR | i; + + if (uindices) { + if (put_user(reg, uindices)) + return -EFAULT; + uindices++; + } + } + + return n; +} + /* * kvm_riscv_vcpu_num_regs - how many registers do we present via KVM_GET/SET_ONE_REG * @@ -1001,6 +1032,7 @@ unsigned long kvm_riscv_vcpu_num_regs(struct kvm_vcpu *vcpu) res += num_timer_regs(); res += num_fp_f_regs(vcpu); res += num_fp_d_regs(vcpu); + res += num_vector_regs(vcpu); res += num_isa_ext_regs(vcpu); res += num_sbi_ext_regs(); @@ -1045,6 +1077,11 @@ int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu, return ret; uindices += ret; + ret = copy_vector_reg_indices(vcpu, uindices); + if (ret < 0) + return ret; + uindices += ret; + ret = copy_isa_ext_reg_indices(vcpu, uindices); if (ret < 0) return ret;
Add all vector CSRs (vstart, vl, vtype, vcsr, vlenb) in get-reg-list. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- arch/riscv/kvm/vcpu_onereg.c | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)