| Message ID | 20231122053817.3401748-12-quic_gaurkash@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Hardware wrapped key support for qcom ice and ufs | expand |
On Tue, Nov 21, 2023 at 09:38:16PM -0800, Gaurav Kashyap wrote: > The Inline Crypto Engine (ICE) for UFS supports the > Hardware Key Manager (hwkm) to securely manage storage > keys. Enable using this hardware on sm8650. I'm unable to understand why the size of the reg changes based on this motivation. Regards, Bjorn > > Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index bbebe15437aa..b61066210e09 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -763,7 +763,8 @@ rng: rng@10c3000 { > ice: crypto@1d88000 { > compatible = "qcom,sm8650-inline-crypto-engine", > "qcom,inline-crypto-engine"; > - reg = <0 0x01d88000 0 0x8000>; > + reg = <0 0x01d88000 0 0x10000>; > + qcom,ice-use-hwkm; > > clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > }; > -- > 2.25.1 > >
On 12/8/2023 9:21 AM, Bjorn Andersson wrote: > On Tue, Nov 21, 2023 at 09:38:16PM -0800, Gaurav Kashyap wrote: >> The Inline Crypto Engine (ICE) for UFS supports the >> Hardware Key Manager (hwkm) to securely manage storage >> keys. Enable using this hardware on sm8650. > > I'm unable to understand why the size of the reg changes based on this > motivation. > > Regards, > Bjorn > Actual size of register space size is 0x18000 (as per IPCAT). But all registers space are not used. HWKM register offset is start at 0x8000. Hence needed to expand reg map size. >> >> Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> index bbebe15437aa..b61066210e09 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> @@ -763,7 +763,8 @@ rng: rng@10c3000 { >> ice: crypto@1d88000 { >> compatible = "qcom,sm8650-inline-crypto-engine", >> "qcom,inline-crypto-engine"; >> - reg = <0 0x01d88000 0 0x8000>; >> + reg = <0 0x01d88000 0 0x10000>; >> + qcom,ice-use-hwkm; >> >> clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; >> }; >> -- >> 2.25.1 >> >> >
On 11/22/2023 11:08 AM, Gaurav Kashyap wrote: > The Inline Crypto Engine (ICE) for UFS supports the Hardware Key Manager > (hwkm) to securely manage storage keys. Enable using this hardware on > sm8650. Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> --- Reviewed-by: Om Prakash Singh <quic_omprsing@quicinc.com>
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index bbebe15437aa..b61066210e09 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -763,7 +763,8 @@ rng: rng@10c3000 { ice: crypto@1d88000 { compatible = "qcom,sm8650-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x10000>; + qcom,ice-use-hwkm; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; };
The Inline Crypto Engine (ICE) for UFS supports the Hardware Key Manager (hwkm) to securely manage storage keys. Enable using this hardware on sm8650. Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)