diff mbox series

[RESEND,v1,1/7] dt-bindings: clock: mpfs: add more MSSPLL output definitions

Message ID 20231208-unripe-maximum-fc77f4967561@spud (mailing list archive)
State Not Applicable
Headers show
Series MPFS clock fixes required for correct CAN clock modeling | expand

Checks

Context Check Description
netdev/tree_selection success Not a local patch

Commit Message

Conor Dooley Dec. 8, 2023, 5:12 p.m. UTC
From: Conor Dooley <conor.dooley@microchip.com>

There are 3 undocumented outputs of the MSSPLL that are used for the CAN
bus, "user crypto" module and eMMC. Add their clock IDs so that they can
be hooked up in DT.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 include/dt-bindings/clock/microchip,mpfs-clock.h | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Emil Renner Berthing Dec. 8, 2023, 5:40 p.m. UTC | #1
Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> There are 3 undocumented outputs of the MSSPLL that are used for the CAN
> bus, "user crypto" module and eMMC. Add their clock IDs so that they can
> be hooked up in DT.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  include/dt-bindings/clock/microchip,mpfs-clock.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h
> index 79775a5134ca..b52f19a2b480 100644
> --- a/include/dt-bindings/clock/microchip,mpfs-clock.h
> +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h
> @@ -44,6 +44,11 @@
>
>  #define CLK_RTCREF	33
>  #define CLK_MSSPLL	34
> +#define CLK_MSSPLL0	34

You add this new CLK_MSSPLL0 macro with the same value as CLK_MSSPLL, but
never seem to use it in this series. Did you mean to rename the CLK_MSSPLL
instances CLK_MSSPLL0?

> +#define CLK_MSSPLL1	35
> +#define CLK_MSSPLL2	36
> +#define CLK_MSSPLL3	37
> +/* 38 is reserved for MSS PLL internals */
>
>  /* Clock Conditioning Circuitry Clock IDs */
>
> --
> 2.39.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Conor Dooley Dec. 8, 2023, 7:26 p.m. UTC | #2
On Fri, Dec 08, 2023 at 09:40:00AM -0800, Emil Renner Berthing wrote:
> Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > There are 3 undocumented outputs of the MSSPLL that are used for the CAN
> > bus, "user crypto" module and eMMC. Add their clock IDs so that they can
> > be hooked up in DT.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> >  include/dt-bindings/clock/microchip,mpfs-clock.h | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h
> > index 79775a5134ca..b52f19a2b480 100644
> > --- a/include/dt-bindings/clock/microchip,mpfs-clock.h
> > +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h
> > @@ -44,6 +44,11 @@
> >
> >  #define CLK_RTCREF	33
> >  #define CLK_MSSPLL	34
> > +#define CLK_MSSPLL0	34
> 
> You add this new CLK_MSSPLL0 macro with the same value as CLK_MSSPLL, but
> never seem to use it in this series. Did you mean to rename the CLK_MSSPLL
> instances CLK_MSSPLL0?

Yes, that was my intention.
Krzysztof Kozlowski Dec. 9, 2023, 7:58 a.m. UTC | #3
On 08/12/2023 18:12, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> There are 3 undocumented outputs of the MSSPLL that are used for the CAN
> bus, "user crypto" module and eMMC. Add their clock IDs so that they can
> be hooked up in DT.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h
index 79775a5134ca..b52f19a2b480 100644
--- a/include/dt-bindings/clock/microchip,mpfs-clock.h
+++ b/include/dt-bindings/clock/microchip,mpfs-clock.h
@@ -44,6 +44,11 @@ 
 
 #define CLK_RTCREF	33
 #define CLK_MSSPLL	34
+#define CLK_MSSPLL0	34
+#define CLK_MSSPLL1	35
+#define CLK_MSSPLL2	36
+#define CLK_MSSPLL3	37
+/* 38 is reserved for MSS PLL internals */
 
 /* Clock Conditioning Circuitry Clock IDs */