| Message ID | 20231214105243.3707730-11-tudor.ambarus@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | GS101 Oriole: CMU_PERIC0 support and USI updates | expand |
On Thu, Dec 14, 2023 at 4:53 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > USI8 I2C is used to communicate with an eeprom found on the battery > connector. Define USI8 in I2C configuration. > > USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 > doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the > selection of the protocol is intentionally left for the board dtsi file. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 26 ++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > index ffb7b4d89a8c..4ea1b180cd0a 100644 > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -354,6 +354,32 @@ pinctrl_peric0: pinctrl@10840000 { > interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; > }; > > + usi8: usi@109700c0 { > + compatible = "google,gs101-usi", > + "samsung,exynos850-usi"; > + reg = <0x109700c0 0x20>; > + ranges; > + #address-cells = <1>; > + #size-cells = <1>; > + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_USI8_USI>, Are you sure this is a leaf clock? Usually it's a GATE clock, not a DIV one. > + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; Because of following letter-for-letter the crazy TRM clock namings, now it's not possible to keep 80 characters length in a sane way :( > + clock-names = "pclk", "ipclk"; > + samsung,sysreg = <&sysreg_peric0 0x101c>; samsung,mode is not needed in this case? > + status = "disabled"; > + > + hsi2c_8: i2c@10970000 { > + compatible = "google,gs101-hsi2c", > + "samsung,exynosautov9-hsi2c"; > + reg = <0x10970000 0xc0>; > + interrupts = <GIC_SPI 642 > + IRQ_TYPE_LEVEL_HIGH 0>; IRQ type constant can fit the previous line. > + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_USI8_USI>, > + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; > + clock-names = "hsi2c", "hsi2c_pclk"; > + status = "disabled"; Pinctrl properties are not needed for this node? > + }; > + }; > + > usi_uart: usi@10a000c0 { > compatible = "google,gs101-usi", > "samsung,exynos850-usi"; > -- > 2.43.0.472.g3155946c3a-goog >
On 14/12/2023 11:52, Tudor Ambarus wrote: > USI8 I2C is used to communicate with an eeprom found on the battery > connector. Define USI8 in I2C configuration. > > USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 > doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the > selection of the protocol is intentionally left for the board dtsi file. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 26 ++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > index ffb7b4d89a8c..4ea1b180cd0a 100644 > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -354,6 +354,32 @@ pinctrl_peric0: pinctrl@10840000 { > interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; > }; > > + usi8: usi@109700c0 { > + compatible = "google,gs101-usi", > + "samsung,exynos850-usi"; > + reg = <0x109700c0 0x20>; > + ranges; > + #address-cells = <1>; > + #size-cells = <1>; > + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_USI8_USI>, > + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; > + clock-names = "pclk", "ipclk"; > + samsung,sysreg = <&sysreg_peric0 0x101c>; > + status = "disabled"; > + > + hsi2c_8: i2c@10970000 { > + compatible = "google,gs101-hsi2c", > + "samsung,exynosautov9-hsi2c"; > + reg = <0x10970000 0xc0>; > + interrupts = <GIC_SPI 642 > + IRQ_TYPE_LEVEL_HIGH 0>; This can be in one line. Limit of 80 is not a hard-limit. It can be violated if it improves readability. Especially if is about 1 character only. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index ffb7b4d89a8c..4ea1b180cd0a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -354,6 +354,32 @@ pinctrl_peric0: pinctrl@10840000 { interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; }; + usi8: usi@109700c0 { + compatible = "google,gs101-usi", + "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_USI8_USI>, + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x101c>; + status = "disabled"; + + hsi2c_8: i2c@10970000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + interrupts = <GIC_SPI 642 + IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_USI8_USI>, + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + usi_uart: usi@10a000c0 { compatible = "google,gs101-usi", "samsung,exynos850-usi";
USI8 I2C is used to communicate with an eeprom found on the battery connector. Define USI8 in I2C configuration. USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the selection of the protocol is intentionally left for the board dtsi file. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 26 ++++++++++++++++++++ 1 file changed, 26 insertions(+)