diff mbox series

[v3,net-next,3/3] amd-xgbe: use smn functions to avoid race

Message ID 20231212053723.443772-4-Raju.Rangoju@amd.com (mailing list archive)
State Changes Requested
Delegated to: Netdev Maintainers
Headers show
Series amd-xgbe: add support for AMD Crater | expand

Checks

Context Check Description
netdev/series_format success Posting correctly formatted
netdev/tree_selection success Clearly marked for net-next
netdev/ynl success Generated files up to date; no warnings/errors; no diff in generated;
netdev/fixes_present success Fixes tag not required for -next series
netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 1115 this patch: 1115
netdev/cc_maintainers success CCed 5 of 5 maintainers
netdev/build_clang success Errors and warnings before: 1142 this patch: 1142
netdev/verify_signedoff success Signed-off-by tag matches author and committer
netdev/deprecated_api success None detected
netdev/check_selftest success No net selftest shell script
netdev/verify_fixes success No Fixes tag
netdev/build_allmodconfig_warn success Errors and warnings before: 1143 this patch: 1143
netdev/checkpatch warning WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? WARNING: line length of 86 exceeds 80 columns WARNING: line length of 97 exceeds 80 columns
netdev/build_clang_rust success No Rust files in patch. Skipping build
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/source_inline success Was 0 now: 0

Commit Message

Raju Rangoju Dec. 12, 2023, 5:37 a.m. UTC
Some of the ethernet add-in-cards have dual PHY but share a single MDIO
line (between the ports). In such cases, link inconsistencies are
noticed during the heavy traffic and during reboot stress tests.

So, use the SMN calls to avoid the race conditions.

Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
---
 drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 33 ++++++------------------
 drivers/net/ethernet/amd/xgbe/xgbe-pci.c | 10 +++----
 drivers/net/ethernet/amd/xgbe/xgbe-smn.h | 27 +++++++++++++++++++
 drivers/net/ethernet/amd/xgbe/xgbe.h     |  2 +-
 4 files changed, 41 insertions(+), 31 deletions(-)
 create mode 100644 drivers/net/ethernet/amd/xgbe/xgbe-smn.h

Comments

Tom Lendacky Dec. 12, 2023, 3:38 p.m. UTC | #1
On 12/11/23 23:37, Raju Rangoju wrote:
> Some of the ethernet add-in-cards have dual PHY but share a single MDIO
> line (between the ports). In such cases, link inconsistencies are
> noticed during the heavy traffic and during reboot stress tests.
> 
> So, use the SMN calls to avoid the race conditions.

So this patch replaces all the PCI accesses you added in patch #2, so why 
not just do this from the start?

> 
> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
> ---
>   drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 33 ++++++------------------
>   drivers/net/ethernet/amd/xgbe/xgbe-pci.c | 10 +++----
>   drivers/net/ethernet/amd/xgbe/xgbe-smn.h | 27 +++++++++++++++++++
>   drivers/net/ethernet/amd/xgbe/xgbe.h     |  2 +-
>   4 files changed, 41 insertions(+), 31 deletions(-)
>   create mode 100644 drivers/net/ethernet/amd/xgbe/xgbe-smn.h
> 
> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
> index a9eb2ffa9f73..8d8876ab258c 100644
> --- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
> +++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
> @@ -124,6 +124,7 @@
>   
>   #include "xgbe.h"
>   #include "xgbe-common.h"
> +#include "xgbe-smn.h"
>   
>   static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
>   {
> @@ -1170,14 +1171,9 @@ static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
>   				 int mmd_reg)
>   {
>   	unsigned int mmd_address, index, offset;
> -	struct pci_dev *rdev;
>   	unsigned long flags;
>   	int mmd_data;
>   
> -	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
> -	if (!rdev)
> -		return 0;
> -
>   	mmd_address = get_mmd_address(pdata, mmd_reg);
>   
>   	/* The PCS registers are accessed using mmio. The underlying
> @@ -1192,13 +1188,10 @@ static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
>   	offset = get_index_offset(pdata, mmd_address, &index);
>   
>   	spin_lock_irqsave(&pdata->xpcs_lock, flags);
> -	pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg));
> -	pci_write_config_dword(rdev, 0x64, index);
> -	pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset);
> -	pci_read_config_dword(rdev, 0x64, &mmd_data);
> +	amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
> +	amd_smn_read(0, pdata->smn_base + offset, &mmd_data);
>   	mmd_data = (offset % 4) ? FIELD_GET(XGBE_GEN_HI_MASK, mmd_data) :
>   				  FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
> -	pci_dev_put(rdev);
>   
>   	spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
>   
> @@ -1209,13 +1202,8 @@ static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
>   				   int mmd_reg, int mmd_data)
>   {
>   	unsigned int mmd_address, index, offset, ctr_mmd_data;
> -	struct pci_dev *rdev;
>   	unsigned long flags;
>   
> -	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
> -	if (!rdev)
> -		return;
> -
>   	mmd_address = get_mmd_address(pdata, mmd_reg);
>   
>   	/* The PCS registers are accessed using mmio. The underlying
> @@ -1230,10 +1218,9 @@ static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
>   	offset = get_index_offset(pdata, mmd_address, &index);
>   
>   	spin_lock_irqsave(&pdata->xpcs_lock, flags);
> -	pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg));
> -	pci_write_config_dword(rdev, 0x64, index);
> -	pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset);
> -	pci_read_config_dword(rdev, 0x64, &ctr_mmd_data);
> +	amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
> +	amd_smn_read(0, pdata->smn_base + offset, &ctr_mmd_data);
> +
>   	if (offset % 4) {
>   		ctr_mmd_data = FIELD_PREP(XGBE_GEN_HI_MASK, mmd_data) |
>   			       FIELD_GET(XGBE_GEN_LO_MASK, ctr_mmd_data);
> @@ -1243,12 +1230,8 @@ static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
>   			       FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
>   	}
>   
> -	pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg));
> -	pci_write_config_dword(rdev, 0x64, index);
> -	pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + offset));
> -	pci_write_config_dword(rdev, 0x64, ctr_mmd_data);
> -	pci_dev_put(rdev);
> -
> +	amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
> +	amd_smn_write(0, (pdata->smn_base + offset), ctr_mmd_data);
>   	spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
>   }
>   
> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
> index db3e8aac3339..135128b5be90 100644
> --- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
> +++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
> @@ -121,6 +121,7 @@
>   
>   #include "xgbe.h"
>   #include "xgbe-common.h"
> +#include "xgbe-smn.h"
>   
>   static int xgbe_config_multi_msi(struct xgbe_prv_data *pdata)
>   {
> @@ -304,18 +305,17 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>   		pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
>   		break;
>   	}
> +	pci_dev_put(rdev);
>   
>   	/* Configure the PCS indirect addressing support */
>   	if (pdata->vdata->xpcs_access == XGBE_XPCS_ACCESS_V3) {
>   		reg = XP_IOREAD(pdata, XP_PROP_0);
> -		pdata->xphy_base = PCS_RN_SMN_BASE_ADDR +
> -				   (PCS_RN_PORT_ADDR_SIZE * XP_GET_BITS(reg, XP_PROP_0, PORT_ID));
> -		pci_write_config_dword(rdev, 0x60, pdata->xphy_base + (pdata->xpcs_window_def_reg));
> -		pci_read_config_dword(rdev, 0x64, &reg);
> +		pdata->smn_base = PCS_RN_SMN_BASE_ADDR +
> +				  (PCS_RN_PORT_ADDR_SIZE * XP_GET_BITS(reg, XP_PROP_0, PORT_ID));
> +		amd_smn_read(0, pdata->smn_base + (pdata->xpcs_window_def_reg), &reg);
>   	} else {
>   		reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
>   	}
> -	pci_dev_put(rdev);
>   
>   	pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
>   	pdata->xpcs_window <<= 6;
> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-smn.h b/drivers/net/ethernet/amd/xgbe/xgbe-smn.h
> new file mode 100644
> index 000000000000..bd25ddc7c869
> --- /dev/null
> +++ b/drivers/net/ethernet/amd/xgbe/xgbe-smn.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * AMD 10Gb Ethernet driver
> + *
> + * Copyright (c) 2023, Advanced Micro Devices, Inc.
> + * All Rights Reserved.
> + *
> + * Author: Raju Rangoju <Raju.Rangoju@amd.com>
> + */

Shouldn't this license match the license in all the other files?

Also, you need header protection here, e.g.:

#ifndef __XGBE_SMN_H__
#define __XGBE_SMN_H__

and a #endif at the end.

Thanks,
Tom

> +
> +#ifdef CONFIG_AMD_NB
> +
> +#include <asm/amd_nb.h>
> +
> +#else
> +
> +static inline int amd_smn_write(u16 node, u32 address, u32 value)
> +{
> +	return -ENODEV;
> +}
> +
> +static inline int amd_smn_read(u16 node, u32 address, u32 *value)
> +{
> +	return -ENODEV;
> +}
> +
> +#endif
> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
> index dbb1faaf6185..ba45ab0adb8c 100644
> --- a/drivers/net/ethernet/amd/xgbe/xgbe.h
> +++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
> @@ -1061,7 +1061,7 @@ struct xgbe_prv_data {
>   	struct device *dev;
>   	struct platform_device *phy_platdev;
>   	struct device *phy_dev;
> -	unsigned int xphy_base;
> +	unsigned int smn_base;
>   
>   	/* Version related data */
>   	struct xgbe_version_data *vdata;
Raju Rangoju Dec. 15, 2023, 4:35 a.m. UTC | #2
On 12/12/2023 9:08 PM, Tom Lendacky wrote:
> On 12/11/23 23:37, Raju Rangoju wrote:
>> Some of the ethernet add-in-cards have dual PHY but share a single MDIO
>> line (between the ports). In such cases, link inconsistencies are
>> noticed during the heavy traffic and during reboot stress tests.
>>
>> So, use the SMN calls to avoid the race conditions.
> 
> So this patch replaces all the PCI accesses you added in patch #2, so 
> why not just do this from the start?

Yes, that is correct. It was done to maintain the history and that will 
be reference as to why SMN is used over regular PCI accesses in this case.

> 
>>
>> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
>> ---
>>   drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 33 ++++++------------------
>>   drivers/net/ethernet/amd/xgbe/xgbe-pci.c | 10 +++----
>>   drivers/net/ethernet/amd/xgbe/xgbe-smn.h | 27 +++++++++++++++++++
>>   drivers/net/ethernet/amd/xgbe/xgbe.h     |  2 +-
>>   4 files changed, 41 insertions(+), 31 deletions(-)
>>   create mode 100644 drivers/net/ethernet/amd/xgbe/xgbe-smn.h
>>
>> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c 
>> b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
>> index a9eb2ffa9f73..8d8876ab258c 100644
>> --- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
>> +++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
>> @@ -124,6 +124,7 @@
>>   #include "xgbe.h"
>>   #include "xgbe-common.h"
>> +#include "xgbe-smn.h"
>>   static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data 
>> *pdata)
>>   {
>> @@ -1170,14 +1171,9 @@ static int xgbe_read_mmd_regs_v3(struct 
>> xgbe_prv_data *pdata, int prtad,
>>                    int mmd_reg)
>>   {
>>       unsigned int mmd_address, index, offset;
>> -    struct pci_dev *rdev;
>>       unsigned long flags;
>>       int mmd_data;
>> -    rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
>> -    if (!rdev)
>> -        return 0;
>> -
>>       mmd_address = get_mmd_address(pdata, mmd_reg);
>>       /* The PCS registers are accessed using mmio. The underlying
>> @@ -1192,13 +1188,10 @@ static int xgbe_read_mmd_regs_v3(struct 
>> xgbe_prv_data *pdata, int prtad,
>>       offset = get_index_offset(pdata, mmd_address, &index);
>>       spin_lock_irqsave(&pdata->xpcs_lock, flags);
>> -    pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + 
>> pdata->xpcs_window_sel_reg));
>> -    pci_write_config_dword(rdev, 0x64, index);
>> -    pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset);
>> -    pci_read_config_dword(rdev, 0x64, &mmd_data);
>> +    amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), 
>> index);
>> +    amd_smn_read(0, pdata->smn_base + offset, &mmd_data);
>>       mmd_data = (offset % 4) ? FIELD_GET(XGBE_GEN_HI_MASK, mmd_data) :
>>                     FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
>> -    pci_dev_put(rdev);
>>       spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
>> @@ -1209,13 +1202,8 @@ static void xgbe_write_mmd_regs_v3(struct 
>> xgbe_prv_data *pdata, int prtad,
>>                      int mmd_reg, int mmd_data)
>>   {
>>       unsigned int mmd_address, index, offset, ctr_mmd_data;
>> -    struct pci_dev *rdev;
>>       unsigned long flags;
>> -    rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
>> -    if (!rdev)
>> -        return;
>> -
>>       mmd_address = get_mmd_address(pdata, mmd_reg);
>>       /* The PCS registers are accessed using mmio. The underlying
>> @@ -1230,10 +1218,9 @@ static void xgbe_write_mmd_regs_v3(struct 
>> xgbe_prv_data *pdata, int prtad,
>>       offset = get_index_offset(pdata, mmd_address, &index);
>>       spin_lock_irqsave(&pdata->xpcs_lock, flags);
>> -    pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + 
>> pdata->xpcs_window_sel_reg));
>> -    pci_write_config_dword(rdev, 0x64, index);
>> -    pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset);
>> -    pci_read_config_dword(rdev, 0x64, &ctr_mmd_data);
>> +    amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), 
>> index);
>> +    amd_smn_read(0, pdata->smn_base + offset, &ctr_mmd_data);
>> +
>>       if (offset % 4) {
>>           ctr_mmd_data = FIELD_PREP(XGBE_GEN_HI_MASK, mmd_data) |
>>                      FIELD_GET(XGBE_GEN_LO_MASK, ctr_mmd_data);
>> @@ -1243,12 +1230,8 @@ static void xgbe_write_mmd_regs_v3(struct 
>> xgbe_prv_data *pdata, int prtad,
>>                      FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
>>       }
>> -    pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + 
>> pdata->xpcs_window_sel_reg));
>> -    pci_write_config_dword(rdev, 0x64, index);
>> -    pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + offset));
>> -    pci_write_config_dword(rdev, 0x64, ctr_mmd_data);
>> -    pci_dev_put(rdev);
>> -
>> +    amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), 
>> index);
>> +    amd_smn_write(0, (pdata->smn_base + offset), ctr_mmd_data);
>>       spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
>>   }
>> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c 
>> b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
>> index db3e8aac3339..135128b5be90 100644
>> --- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
>> +++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
>> @@ -121,6 +121,7 @@
>>   #include "xgbe.h"
>>   #include "xgbe-common.h"
>> +#include "xgbe-smn.h"
>>   static int xgbe_config_multi_msi(struct xgbe_prv_data *pdata)
>>   {
>> @@ -304,18 +305,17 @@ static int xgbe_pci_probe(struct pci_dev *pdev, 
>> const struct pci_device_id *id)
>>           pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
>>           break;
>>       }
>> +    pci_dev_put(rdev);
>>       /* Configure the PCS indirect addressing support */
>>       if (pdata->vdata->xpcs_access == XGBE_XPCS_ACCESS_V3) {
>>           reg = XP_IOREAD(pdata, XP_PROP_0);
>> -        pdata->xphy_base = PCS_RN_SMN_BASE_ADDR +
>> -                   (PCS_RN_PORT_ADDR_SIZE * XP_GET_BITS(reg, 
>> XP_PROP_0, PORT_ID));
>> -        pci_write_config_dword(rdev, 0x60, pdata->xphy_base + 
>> (pdata->xpcs_window_def_reg));
>> -        pci_read_config_dword(rdev, 0x64, &reg);
>> +        pdata->smn_base = PCS_RN_SMN_BASE_ADDR +
>> +                  (PCS_RN_PORT_ADDR_SIZE * XP_GET_BITS(reg, 
>> XP_PROP_0, PORT_ID));
>> +        amd_smn_read(0, pdata->smn_base + 
>> (pdata->xpcs_window_def_reg), &reg);
>>       } else {
>>           reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
>>       }
>> -    pci_dev_put(rdev);
>>       pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
>>       pdata->xpcs_window <<= 6;
>> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-smn.h 
>> b/drivers/net/ethernet/amd/xgbe/xgbe-smn.h
>> new file mode 100644
>> index 000000000000..bd25ddc7c869
>> --- /dev/null
>> +++ b/drivers/net/ethernet/amd/xgbe/xgbe-smn.h
>> @@ -0,0 +1,27 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * AMD 10Gb Ethernet driver
>> + *
>> + * Copyright (c) 2023, Advanced Micro Devices, Inc.
>> + * All Rights Reserved.
>> + *
>> + * Author: Raju Rangoju <Raju.Rangoju@amd.com>
>> + */
> 
> Shouldn't this license match the license in all the other files?
> 
> Also, you need header protection here, e.g.:
> 
> #ifndef __XGBE_SMN_H__
> #define __XGBE_SMN_H__
> 
> and a #endif at the end.

Sure Tom, I'll take care of this.

> 
> Thanks,
> Tom
> 
>> +
>> +#ifdef CONFIG_AMD_NB
>> +
>> +#include <asm/amd_nb.h>
>> +
>> +#else
>> +
>> +static inline int amd_smn_write(u16 node, u32 address, u32 value)
>> +{
>> +    return -ENODEV;
>> +}
>> +
>> +static inline int amd_smn_read(u16 node, u32 address, u32 *value)
>> +{
>> +    return -ENODEV;
>> +}
>> +
>> +#endif
>> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h 
>> b/drivers/net/ethernet/amd/xgbe/xgbe.h
>> index dbb1faaf6185..ba45ab0adb8c 100644
>> --- a/drivers/net/ethernet/amd/xgbe/xgbe.h
>> +++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
>> @@ -1061,7 +1061,7 @@ struct xgbe_prv_data {
>>       struct device *dev;
>>       struct platform_device *phy_platdev;
>>       struct device *phy_dev;
>> -    unsigned int xphy_base;
>> +    unsigned int smn_base;
>>       /* Version related data */
>>       struct xgbe_version_data *vdata;
Tom Lendacky Dec. 15, 2023, 2:35 p.m. UTC | #3
On 12/14/23 22:35, Raju Rangoju wrote:
> 
> 
> On 12/12/2023 9:08 PM, Tom Lendacky wrote:
>> On 12/11/23 23:37, Raju Rangoju wrote:
>>> Some of the ethernet add-in-cards have dual PHY but share a single MDIO
>>> line (between the ports). In such cases, link inconsistencies are
>>> noticed during the heavy traffic and during reboot stress tests.
>>>
>>> So, use the SMN calls to avoid the race conditions.
>>
>> So this patch replaces all the PCI accesses you added in patch #2, so 
>> why not just do this from the start?
> 
> Yes, that is correct. It was done to maintain the history and that will be 
> reference as to why SMN is used over regular PCI accesses in this case.

Seems unnecessary to me. Adding a comment in the commit log and the code 
that states why SMN is used instead of PCI and how it fixes the race 
condition would be enough. Your call... but since patch #2 enables the 
device, this could cause a bisect issue.

Thanks,
Tom

>
diff mbox series

Patch

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index a9eb2ffa9f73..8d8876ab258c 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -124,6 +124,7 @@ 
 
 #include "xgbe.h"
 #include "xgbe-common.h"
+#include "xgbe-smn.h"
 
 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
 {
@@ -1170,14 +1171,9 @@  static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
 				 int mmd_reg)
 {
 	unsigned int mmd_address, index, offset;
-	struct pci_dev *rdev;
 	unsigned long flags;
 	int mmd_data;
 
-	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
-	if (!rdev)
-		return 0;
-
 	mmd_address = get_mmd_address(pdata, mmd_reg);
 
 	/* The PCS registers are accessed using mmio. The underlying
@@ -1192,13 +1188,10 @@  static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
 	offset = get_index_offset(pdata, mmd_address, &index);
 
 	spin_lock_irqsave(&pdata->xpcs_lock, flags);
-	pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg));
-	pci_write_config_dword(rdev, 0x64, index);
-	pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset);
-	pci_read_config_dword(rdev, 0x64, &mmd_data);
+	amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
+	amd_smn_read(0, pdata->smn_base + offset, &mmd_data);
 	mmd_data = (offset % 4) ? FIELD_GET(XGBE_GEN_HI_MASK, mmd_data) :
 				  FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
-	pci_dev_put(rdev);
 
 	spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
 
@@ -1209,13 +1202,8 @@  static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
 				   int mmd_reg, int mmd_data)
 {
 	unsigned int mmd_address, index, offset, ctr_mmd_data;
-	struct pci_dev *rdev;
 	unsigned long flags;
 
-	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
-	if (!rdev)
-		return;
-
 	mmd_address = get_mmd_address(pdata, mmd_reg);
 
 	/* The PCS registers are accessed using mmio. The underlying
@@ -1230,10 +1218,9 @@  static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
 	offset = get_index_offset(pdata, mmd_address, &index);
 
 	spin_lock_irqsave(&pdata->xpcs_lock, flags);
-	pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg));
-	pci_write_config_dword(rdev, 0x64, index);
-	pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset);
-	pci_read_config_dword(rdev, 0x64, &ctr_mmd_data);
+	amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
+	amd_smn_read(0, pdata->smn_base + offset, &ctr_mmd_data);
+
 	if (offset % 4) {
 		ctr_mmd_data = FIELD_PREP(XGBE_GEN_HI_MASK, mmd_data) |
 			       FIELD_GET(XGBE_GEN_LO_MASK, ctr_mmd_data);
@@ -1243,12 +1230,8 @@  static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
 			       FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
 	}
 
-	pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg));
-	pci_write_config_dword(rdev, 0x64, index);
-	pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + offset));
-	pci_write_config_dword(rdev, 0x64, ctr_mmd_data);
-	pci_dev_put(rdev);
-
+	amd_smn_write(0, (pdata->smn_base + pdata->xpcs_window_sel_reg), index);
+	amd_smn_write(0, (pdata->smn_base + offset), ctr_mmd_data);
 	spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
 }
 
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
index db3e8aac3339..135128b5be90 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
@@ -121,6 +121,7 @@ 
 
 #include "xgbe.h"
 #include "xgbe-common.h"
+#include "xgbe-smn.h"
 
 static int xgbe_config_multi_msi(struct xgbe_prv_data *pdata)
 {
@@ -304,18 +305,17 @@  static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 		pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
 		break;
 	}
+	pci_dev_put(rdev);
 
 	/* Configure the PCS indirect addressing support */
 	if (pdata->vdata->xpcs_access == XGBE_XPCS_ACCESS_V3) {
 		reg = XP_IOREAD(pdata, XP_PROP_0);
-		pdata->xphy_base = PCS_RN_SMN_BASE_ADDR +
-				   (PCS_RN_PORT_ADDR_SIZE * XP_GET_BITS(reg, XP_PROP_0, PORT_ID));
-		pci_write_config_dword(rdev, 0x60, pdata->xphy_base + (pdata->xpcs_window_def_reg));
-		pci_read_config_dword(rdev, 0x64, &reg);
+		pdata->smn_base = PCS_RN_SMN_BASE_ADDR +
+				  (PCS_RN_PORT_ADDR_SIZE * XP_GET_BITS(reg, XP_PROP_0, PORT_ID));
+		amd_smn_read(0, pdata->smn_base + (pdata->xpcs_window_def_reg), &reg);
 	} else {
 		reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
 	}
-	pci_dev_put(rdev);
 
 	pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
 	pdata->xpcs_window <<= 6;
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-smn.h b/drivers/net/ethernet/amd/xgbe/xgbe-smn.h
new file mode 100644
index 000000000000..bd25ddc7c869
--- /dev/null
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-smn.h
@@ -0,0 +1,27 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * AMD 10Gb Ethernet driver
+ *
+ * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Author: Raju Rangoju <Raju.Rangoju@amd.com>
+ */
+
+#ifdef CONFIG_AMD_NB
+
+#include <asm/amd_nb.h>
+
+#else
+
+static inline int amd_smn_write(u16 node, u32 address, u32 value)
+{
+	return -ENODEV;
+}
+
+static inline int amd_smn_read(u16 node, u32 address, u32 *value)
+{
+	return -ENODEV;
+}
+
+#endif
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index dbb1faaf6185..ba45ab0adb8c 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -1061,7 +1061,7 @@  struct xgbe_prv_data {
 	struct device *dev;
 	struct platform_device *phy_platdev;
 	struct device *phy_dev;
-	unsigned int xphy_base;
+	unsigned int smn_base;
 
 	/* Version related data */
 	struct xgbe_version_data *vdata;