| Message ID | 20231214062847.2215542-8-quic_ipkumar@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add PCIe support for Qualcomm IPQ5332 | expand |
On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > Add support for the PCIe controller on the Qualcomm > IPQ5332 SoC to the bindings. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index eadba38171e1..af5e67d2a984 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -21,6 +21,7 @@ properties: > - qcom,pcie-apq8064 > - qcom,pcie-apq8084 > - qcom,pcie-ipq4019 > + - qcom,pcie-ipq5332 > - qcom,pcie-ipq6018 > - qcom,pcie-ipq8064 > - qcom,pcie-ipq8064-v2 > @@ -170,6 +171,7 @@ allOf: > compatible: > contains: > enum: > + - qcom,pcie-ipq5332 > - qcom,pcie-ipq6018 > - qcom,pcie-ipq8074-gen3 > then: > @@ -332,6 +334,39 @@ allOf: > - const: ahb # AHB reset > - const: phy_ahb # PHY AHB reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-ipq5332 As you seem to be depending on the ipq9574, could you please reuse the DT entry too? > + then: > + properties: > + clocks: > + minItems: 6 > + maxItems: 6 > + clock-names: > + items: > + - const: ahb # AHB clock > + - const: aux # Auxiliary clock > + - const: axi_m # AXI Master clock > + - const: axi_s # AXI Slave clock > + - const: axi_bridge # AXI bridge clock > + - const: rchng > + resets: > + minItems: 8 > + maxItems: 8 > + reset-names: > + items: > + - const: pipe # PIPE reset > + - const: sticky # Core sticky reset > + - const: axi_m_sticky # AXI master sticky reset > + - const: axi_m # AXI master reset > + - const: axi_s_sticky # AXI slave sticky reset > + - const: axi_s # AXI slave reset > + - const: ahb # AHB reset > + - const: aux # AUX reset > + > - if: > properties: > compatible: > @@ -790,6 +825,7 @@ allOf: > enum: > - qcom,pcie-apq8064 > - qcom,pcie-ipq4019 > + - qcom,pcie-ipq5332 > - qcom,pcie-ipq8064 > - qcom,pcie-ipq8064v2 > - qcom,pcie-ipq8074 > -- > 2.34.1 > >
On 12/14/2023 12:45 PM, Dmitry Baryshkov wrote: > On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: >> Add support for the PCIe controller on the Qualcomm >> IPQ5332 SoC to the bindings. >> >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >> --- >> .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++ >> 1 file changed, 36 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> index eadba38171e1..af5e67d2a984 100644 >> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> @@ -21,6 +21,7 @@ properties: >> - qcom,pcie-apq8064 >> - qcom,pcie-apq8084 >> - qcom,pcie-ipq4019 >> + - qcom,pcie-ipq5332 >> - qcom,pcie-ipq6018 >> - qcom,pcie-ipq8064 >> - qcom,pcie-ipq8064-v2 >> @@ -170,6 +171,7 @@ allOf: >> compatible: >> contains: >> enum: >> + - qcom,pcie-ipq5332 >> - qcom,pcie-ipq6018 >> - qcom,pcie-ipq8074-gen3 >> then: >> @@ -332,6 +334,39 @@ allOf: >> - const: ahb # AHB reset >> - const: phy_ahb # PHY AHB reset >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,pcie-ipq5332 > As you seem to be depending on the ipq9574, could you please reuse the > DT entry too? Sure, will reuse ipq9574 entry. >> + then: >> + properties: >> + clocks: >> + minItems: 6 >> + maxItems: 6 >> + clock-names: >> + items: >> + - const: ahb # AHB clock >> + - const: aux # Auxiliary clock >> + - const: axi_m # AXI Master clock >> + - const: axi_s # AXI Slave clock >> + - const: axi_bridge # AXI bridge clock >> + - const: rchng >> + resets: >> + minItems: 8 >> + maxItems: 8 >> + reset-names: >> + items: >> + - const: pipe # PIPE reset >> + - const: sticky # Core sticky reset >> + - const: axi_m_sticky # AXI master sticky reset >> + - const: axi_m # AXI master reset >> + - const: axi_s_sticky # AXI slave sticky reset >> + - const: axi_s # AXI slave reset >> + - const: ahb # AHB reset >> + - const: aux # AUX reset >> + >> - if: >> properties: >> compatible: >> @@ -790,6 +825,7 @@ allOf: >> enum: >> - qcom,pcie-apq8064 >> - qcom,pcie-ipq4019 >> + - qcom,pcie-ipq5332 >> - qcom,pcie-ipq8064 >> - qcom,pcie-ipq8064v2 >> - qcom,pcie-ipq8074 >> -- >> 2.34.1 >> >> > -- Thanks, Praveenkumar
On 14/12/2023 07:28, Praveenkumar I wrote: > Add support for the PCIe controller on the Qualcomm > IPQ5332 SoC to the bindings. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index eadba38171e1..af5e67d2a984 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -21,6 +21,7 @@ properties: > - qcom,pcie-apq8064 > - qcom,pcie-apq8084 > - qcom,pcie-ipq4019 > + - qcom,pcie-ipq5332 > - qcom,pcie-ipq6018 > - qcom,pcie-ipq8064 > - qcom,pcie-ipq8064-v2 > @@ -170,6 +171,7 @@ allOf: > compatible: > contains: > enum: > + - qcom,pcie-ipq5332 > - qcom,pcie-ipq6018 > - qcom,pcie-ipq8074-gen3 > then: > @@ -332,6 +334,39 @@ allOf: > - const: ahb # AHB reset > - const: phy_ahb # PHY AHB reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-ipq5332 > + then: > + properties: > + clocks: > + minItems: 6 > + maxItems: 6 > + clock-names: > + items: > + - const: ahb # AHB clock > + - const: aux # Auxiliary clock > + - const: axi_m # AXI Master clock > + - const: axi_s # AXI Slave clock > + - const: axi_bridge # AXI bridge clock > + - const: rchng > + resets: > + minItems: 8 > + maxItems: 8 > + reset-names: > + items: > + - const: pipe # PIPE reset No sleep reset? Otherwise it looks like some existing entry, so you should use the same order of resets. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index eadba38171e1..af5e67d2a984 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -170,6 +171,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 then: @@ -332,6 +334,39 @@ allOf: - const: ahb # AHB reset - const: phy_ahb # PHY AHB reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq5332 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: axi_bridge # AXI bridge clock + - const: rchng + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sticky # Core sticky reset + - const: axi_m_sticky # AXI master sticky reset + - const: axi_m # AXI master reset + - const: axi_s_sticky # AXI slave sticky reset + - const: axi_s # AXI slave reset + - const: ahb # AHB reset + - const: aux # AUX reset + - if: properties: compatible: @@ -790,6 +825,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074
Add support for the PCIe controller on the Qualcomm IPQ5332 SoC to the bindings. Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> --- .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+)