| Message ID | 20231216135136.1597456-1-me@deliversmonkey.space (mailing list archive) |
|---|---|
| Headers | show |
| Series | Pointer Masking update to Zjpm v0.6.1 | expand |
On Sat, Dec 16, 2023 at 11:52 PM Alexey Baturo <baturo.alexey@gmail.com> wrote: > > From: Alexey Baturo <baturo.alexey@gmail.com> > > Hi all, > > It looks like Zjpm v0.8 is almost frozen and we don't expect it change drastically anymore. > Compared to the original implementation with explicit base and mask CSRs, we now only have > several fixed options for number of masked bits which are set using existing CSRs. > > Thanks > > [previous:] > > This series of patches intends to update RISC-V Pointer Masking implementation > to the latest Zjpm v0.6.1 version. > The Pointer Masking functionality is simplified compared to previous version > of spec. > The changes have been tested with handwritten assembly tests and LLVM HWASAN > test suite. > > Thanks > > Alexey Baturo (6): > target/riscv: Remove obsolete pointer masking extension code. > target/riscv: Add new CSR fields for S{sn,mn,m}pm extensions as part > of Zjpm v0.8 > target/riscv: Add pointer masking tb flags > target/riscv: Add functions to calculate current number of masked bits > for pointer masking > target/riscv: Update address modify functions to take into account > pointer masking > target/riscv: Enable updates for pointer masking variables and thus > enable pointer masking extension > > target/riscv/cpu.c | 17 +- > target/riscv/cpu.h | 35 ++-- > target/riscv/cpu_bits.h | 85 +-------- > target/riscv/cpu_cfg.h | 3 + > target/riscv/cpu_helper.c | 85 +++++---- > target/riscv/csr.c | 339 ++--------------------------------- > target/riscv/machine.c | 14 +- > target/riscv/pmp.c | 14 +- > target/riscv/pmp.h | 11 +- > target/riscv/translate.c | 50 +++--- > target/riscv/vector_helper.c | 9 +- > 11 files changed, 143 insertions(+), 519 deletions(-) Overall it looks good! Alistair > > -- > 2.34.1 > >
From: Alexey Baturo <baturo.alexey@gmail.com> Hi all, It looks like Zjpm v0.8 is almost frozen and we don't expect it change drastically anymore. Compared to the original implementation with explicit base and mask CSRs, we now only have several fixed options for number of masked bits which are set using existing CSRs. Thanks [previous:] This series of patches intends to update RISC-V Pointer Masking implementation to the latest Zjpm v0.6.1 version. The Pointer Masking functionality is simplified compared to previous version of spec. The changes have been tested with handwritten assembly tests and LLVM HWASAN test suite. Thanks Alexey Baturo (6): target/riscv: Remove obsolete pointer masking extension code. target/riscv: Add new CSR fields for S{sn,mn,m}pm extensions as part of Zjpm v0.8 target/riscv: Add pointer masking tb flags target/riscv: Add functions to calculate current number of masked bits for pointer masking target/riscv: Update address modify functions to take into account pointer masking target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension target/riscv/cpu.c | 17 +- target/riscv/cpu.h | 35 ++-- target/riscv/cpu_bits.h | 85 +-------- target/riscv/cpu_cfg.h | 3 + target/riscv/cpu_helper.c | 85 +++++---- target/riscv/csr.c | 339 ++--------------------------------- target/riscv/machine.c | 14 +- target/riscv/pmp.c | 14 +- target/riscv/pmp.h | 11 +- target/riscv/translate.c | 50 +++--- target/riscv/vector_helper.c | 9 +- 11 files changed, 143 insertions(+), 519 deletions(-)