| Message ID | 1700533494-19276-2-git-send-email-quic_taozha@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3,1/8] dt-bindings: arm: Add support for CMB element size | expand |
On 21/11/2023 03:24, Tao Zhang wrote: > Add property "qcom,cmb-elem-size" to support CMB(Continuous > Multi-Bit) element for TPDM. The associated aggregator will read > this size before it is enabled. CMB element size currently only > supports 32-bit and 64-bit. > qcom,dsb-msrs-num: > description: > Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) > @@ -110,4 +119,23 @@ examples: > }; > }; > > + tpdm@6c29000 { > + compatible = "qcom,coresight-tpdm", "arm,primecell"; > + reg = <0x06c29000 0x1000>; > + reg-names = "tpdm-base"; > + > + qcom,cmb-element-size = /bits/ 8 <64>; One new property usually does not justify new example. Why it cannot be added to existing example? Anyway, I prefer not to take any new Qualcomm Coresight bindings or Qualcomm SoC DTS nodes with Coresight till we fix all existing warnings. I don't know how to fix them, so I need help with them. No such fixing happened so far from Qcom, so pushback is my only way to get any attention. I already commented on this in other email thread. Best regards, Krzysztof
On 21/11/2023 02:24, Tao Zhang wrote: > Add property "qcom,cmb-elem-size" to support CMB(Continuous > Multi-Bit) element for TPDM. The associated aggregator will read > this size before it is enabled. CMB element size currently only > supports 32-bit and 64-bit. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> > --- > .../bindings/arm/qcom,coresight-tpdm.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > index 61ddc3b5b247..0d9fe01a8b15 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > @@ -52,6 +52,15 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint8 > enum: [32, 64] > > + qcom,cmb-element-size: > + description: > + Specifies the CMB(Continuous Multi-Bit) element size supported by > + the monitor. The associated aggregator will read this size before it > + is enabled. CMB element size currently only supports 8-bit, 32-bit > + and 64-bit. > + $ref: /schemas/types.yaml#/definitions/uint8 > + enum: [8, 32, 64] > + > qcom,dsb-msrs-num: > description: > Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) > @@ -110,4 +119,23 @@ examples: > }; > }; > > + tpdm@6c29000 { > + compatible = "qcom,coresight-tpdm", "arm,primecell"; > + reg = <0x06c29000 0x1000>; > + reg-names = "tpdm-base"; I think this one gives this error: $ make dt_binding_check DT_SCHEMA_FILES=arm/qcom,coresight DTC_CHK Documentation/devicetree/bindings/arm/qcom,coresight- tpdm.example.dtb qcom,coresight-tpdm.example.dtb: tpdm@6c29000: 'reg-names' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas /arm/qcom,coresight-tpdm.yaml# > + > + qcom,cmb-element-size = /bits/ 8 <64>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + tpdm_ipcc_out_funnel_center: endpoint { > + remote-endpoint = > + <&funnel_center_in_tpdm_ipcc>; > + }; > + }; > + }; > + }; > ...
On 12/15/2023 7:19 PM, James Clark wrote: > > On 21/11/2023 02:24, Tao Zhang wrote: >> Add property "qcom,cmb-elem-size" to support CMB(Continuous >> Multi-Bit) element for TPDM. The associated aggregator will read >> this size before it is enabled. CMB element size currently only >> supports 32-bit and 64-bit. >> >> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> >> --- >> .../bindings/arm/qcom,coresight-tpdm.yaml | 28 +++++++++++++++++++ >> 1 file changed, 28 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> index 61ddc3b5b247..0d9fe01a8b15 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> @@ -52,6 +52,15 @@ properties: >> $ref: /schemas/types.yaml#/definitions/uint8 >> enum: [32, 64] >> >> + qcom,cmb-element-size: >> + description: >> + Specifies the CMB(Continuous Multi-Bit) element size supported by >> + the monitor. The associated aggregator will read this size before it >> + is enabled. CMB element size currently only supports 8-bit, 32-bit >> + and 64-bit. >> + $ref: /schemas/types.yaml#/definitions/uint8 >> + enum: [8, 32, 64] >> + >> qcom,dsb-msrs-num: >> description: >> Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) >> @@ -110,4 +119,23 @@ examples: >> }; >> }; >> >> + tpdm@6c29000 { >> + compatible = "qcom,coresight-tpdm", "arm,primecell"; >> + reg = <0x06c29000 0x1000>; >> + reg-names = "tpdm-base"; > I think this one gives this error: > > $ make dt_binding_check DT_SCHEMA_FILES=arm/qcom,coresight > > DTC_CHK Documentation/devicetree/bindings/arm/qcom,coresight- > tpdm.example.dtb > qcom,coresight-tpdm.example.dtb: tpdm@6c29000: 'reg-names' does not > match any of the regexes: 'pinctrl-[0-9]+' > from schema $id: http://devicetree.org/schemas > /arm/qcom,coresight-tpdm.yaml# I will fix this in the next patch series. Best, Tao >> + >> + qcom,cmb-element-size = /bits/ 8 <64>; >> + >> + clocks = <&aoss_qmp>; >> + clock-names = "apb_pclk"; >> + >> + out-ports { >> + port { >> + tpdm_ipcc_out_funnel_center: endpoint { >> + remote-endpoint = >> + <&funnel_center_in_tpdm_ipcc>; >> + }; >> + }; >> + }; >> + }; >> ...
On 11/21/2023 3:24 PM, Krzysztof Kozlowski wrote: > On 21/11/2023 03:24, Tao Zhang wrote: >> Add property "qcom,cmb-elem-size" to support CMB(Continuous >> Multi-Bit) element for TPDM. The associated aggregator will read >> this size before it is enabled. CMB element size currently only >> supports 32-bit and 64-bit. > >> qcom,dsb-msrs-num: >> description: >> Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) >> @@ -110,4 +119,23 @@ examples: >> }; >> }; >> >> + tpdm@6c29000 { >> + compatible = "qcom,coresight-tpdm", "arm,primecell"; >> + reg = <0x06c29000 0x1000>; >> + reg-names = "tpdm-base"; >> + >> + qcom,cmb-element-size = /bits/ 8 <64>; > One new property usually does not justify new example. Why it cannot be > added to existing example? Because the existing example tpdm "tpdm@684c000" which only supports dsb sub-unit. Most TPDMs only support one type of sub-unit. > > Anyway, I prefer not to take any new Qualcomm Coresight bindings or > Qualcomm SoC DTS nodes with Coresight till we fix all existing warnings. > I don't know how to fix them, so I need help with them. No such fixing > happened so far from Qcom, so pushback is my only way to get any attention. > > I already commented on this in other email thread. Jinlong has fixed the warnings from coresight bindings. I will prepare my next patch series soon. Best, Tao > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 61ddc3b5b247..0d9fe01a8b15 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -52,6 +52,15 @@ properties: $ref: /schemas/types.yaml#/definitions/uint8 enum: [32, 64] + qcom,cmb-element-size: + description: + Specifies the CMB(Continuous Multi-Bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. CMB element size currently only supports 8-bit, 32-bit + and 64-bit. + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [8, 32, 64] + qcom,dsb-msrs-num: description: Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) @@ -110,4 +119,23 @@ examples: }; }; + tpdm@6c29000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x06c29000 0x1000>; + reg-names = "tpdm-base"; + + qcom,cmb-element-size = /bits/ 8 <64>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_out_funnel_center: endpoint { + remote-endpoint = + <&funnel_center_in_tpdm_ipcc>; + }; + }; + }; + }; ...